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serial: lpuart: Enable RX and TX FIFO 

Enable the RX and TX FIFO in LPUART driver to avoid the input lost
during U-Boot boot up.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Ye Li 2018-10-18 14:28:32 +02:00 committed by Stefano Babic
parent 126f884903
commit cdc16f6182
1 changed files with 26 additions and 7 deletions
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33
drivers/serial/serial_lpuart.c
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@ -40,6 +40,12 @@
#define CTRL_TE (1 << 19) #define CTRL_TE (1 << 19)
#define CTRL_RE (1 << 18) #define CTRL_RE (1 << 18)
#define FIFO_RXFLUSH BIT(14)
#define FIFO_TXFLUSH BIT(15)
#define FIFO_TXSIZE_MASK 0x70
#define FIFO_TXSIZE_OFF 4
#define FIFO_RXSIZE_MASK 0x7
#define FIFO_RXSIZE_OFF 0
#define FIFO_TXFE 0x80 #define FIFO_TXFE 0x80
#ifdef CONFIG_ARCH_IMX8 #ifdef CONFIG_ARCH_IMX8
#define FIFO_RXFE 0x08 #define FIFO_RXFE 0x08
@ -47,7 +53,7 @@
#define FIFO_RXFE 0x40 #define FIFO_RXFE 0x40
#endif #endif
#define WATER_TXWATER_OFF 1 #define WATER_TXWATER_OFF 0
#define WATER_RXWATER_OFF 16 #define WATER_RXWATER_OFF 16
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -318,15 +324,28 @@ static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat) static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
{ {
struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg; struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
u32 ctrl; u32 val, tx_fifo_size;
lpuart_read32(plat->flags, &base->ctrl, &ctrl); lpuart_read32(plat->flags, &base->ctrl, &val);
ctrl &= ~CTRL_RE; val &= ~CTRL_RE;
ctrl &= ~CTRL_TE; val &= ~CTRL_TE;
lpuart_write32(plat->flags, &base->ctrl, ctrl); lpuart_write32(plat->flags, &base->ctrl, val);
lpuart_write32(plat->flags, &base->modir, 0); lpuart_write32(plat->flags, &base->modir, 0);
lpuart_write32(plat->flags, &base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
lpuart_read32(plat->flags, &base->fifo, &val);
tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
/* Set the TX water to half of FIFO size */
if (tx_fifo_size > 1)
tx_fifo_size = tx_fifo_size >> 1;
/* Set RX water to 0, to be triggered by any receive data */
lpuart_write32(plat->flags, &base->water,
(tx_fifo_size << WATER_TXWATER_OFF));
/* Enable TX and RX FIFO */
val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
lpuart_write32(plat->flags, &base->fifo, val);
lpuart_write32(plat->flags, &base->match, 0); lpuart_write32(plat->flags, &base->match, 0);