Merge git://git.denx.de/u-boot-ti

arch/arm/cpu/armv7/am33xx/sys_info.c

@@ -18,6 +18,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <power/tps65910.h>
+#include <linux/compiler.h>
 
 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
 
@@ -51,11 +52,11 @@ u32 get_cpu_type(void)
 
 /**
  * get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ * returns: 0 for the ATAG REVISION tag value.
  */
-u32 get_board_rev(void)
+u32 __weak get_board_rev(void)
 {
-	return BOARD_REV_ID;
+	return 0;
 }
 
 /**

arch/arm/cpu/armv7/omap3/Kconfig

@@ -22,6 +22,9 @@ config TARGET_CM_T35
 	bool "CompuLab CM-T3530 and CM-T3730 boards"
 	select SUPPORT_SPL
 
+config TARGET_CM_T3517
+	bool "CompuLab CM-T3517 boards"
+
 config TARGET_DEVKIT8000
 	bool "TimLL OMAP3 Devkit8000"
 	select SUPPORT_SPL
@@ -98,6 +101,7 @@ source "board/teejet/mt_ventoux/Kconfig"
 source "board/ti/sdp3430/Kconfig"
 source "board/ti/beagle/Kconfig"
 source "board/compulab/cm_t35/Kconfig"
+source "board/compulab/cm_t3517/Kconfig"
 source "board/timll/devkit8000/Kconfig"
 source "board/ti/evm/Kconfig"
 source "board/isee/igep00x0/Kconfig"

arch/arm/include/asm/arch-am33xx/sys_proto.h

@@ -14,8 +14,6 @@
 #include <asm/ti-common/sys_proto.h>
 #include <asm/arch/cpu.h>
 
-#define BOARD_REV_ID	0x0
-
 u32 get_cpu_rev(void);
 u32 get_sysboot_value(void);
 

arch/arm/include/asm/arch-keystone/hardware-k2e.h

@@ -57,8 +57,6 @@
 #define KS2_NETCP_PDMA_SCHED_BASE	0x24186100
 #define KS2_NETCP_PDMA_RX_FLOW_BASE	0x24189000
 #define KS2_NETCP_PDMA_RX_FLOW_NUM	96
-#define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
-#define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
 #define KS2_NETCP_PDMA_TX_SND_QUEUE	896
 
 /* NETCP */

arch/arm/include/asm/arch-keystone/hardware-k2hk.h

@@ -98,8 +98,6 @@
 #define KS2_NETCP_PDMA_SCHED_BASE	0x02004c00
 #define KS2_NETCP_PDMA_RX_FLOW_BASE	0x02005000
 #define KS2_NETCP_PDMA_RX_FLOW_NUM	32
-#define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
-#define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
 #define KS2_NETCP_PDMA_TX_SND_QUEUE	648
 
 /* NETCP */

arch/arm/include/asm/arch-keystone/hardware-k2l.h

@@ -84,6 +84,10 @@
 /* OSR memory size */
 #define KS2_OSR_SIZE			0x100000
 
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE		0x02320000
+#define KS2_LANES_PER_SGMII_SERDES	2
+
 /* Number of DSP cores */
 #define KS2_NUM_DSPS			4
 
@@ -98,4 +102,7 @@
 #define KS2_NETCP_PDMA_RX_FLOW_NUM	96
 #define KS2_NETCP_PDMA_TX_SND_QUEUE	896
 
+/* NETCP */
+#define KS2_NETCP_BASE			0x26000000
+
 #endif /* __ASM_ARCH_HARDWARE_K2L_H */

arch/arm/include/asm/arch-keystone/hardware.h

@@ -122,6 +122,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_EDMA_QEESR			0x108c
 #define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
 
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
+
 /* Chip Interrupt Controller */
 #define KS2_CIC2_BASE			0x02608000
 

board/compulab/cm_t35/cm_t35.c

@@ -19,12 +19,11 @@
 #include <i2c.h>
 #include <usb.h>
 #include <mmc.h>
-#include <nand.h>
 #include <twl4030.h>
-#include <bmp_layout.h>
 #include <linux/compiler.h>
 
 #include <asm/io.h>
+#include <asm/errno.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/mmc_host_def.h>
@@ -33,6 +32,7 @@
 #include <asm/ehci-omap.h>
 #include <asm/gpio.h>
 
+#include "../common/common.h"
 #include "../common/eeprom.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -43,58 +43,6 @@ const omap3_sysinfo sysinfo = {
 	"NAND",
 };
 
-static u32 gpmc_net_config[GPMC_MAX_REG] = {
-	NET_GPMC_CONFIG1,
-	NET_GPMC_CONFIG2,
-	NET_GPMC_CONFIG3,
-	NET_GPMC_CONFIG4,
-	NET_GPMC_CONFIG5,
-	NET_GPMC_CONFIG6,
-	0
-};
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_CMD_NAND
-static int splash_load_from_nand(u32 bmp_load_addr)
-{
-	struct bmp_header *bmp_hdr;
-	int res, splash_screen_nand_offset = 0x100000;
-	size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
-
-	if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
-		goto splash_address_too_high;
-
-	res = nand_read_skip_bad(&nand_info[nand_curr_device],
-			splash_screen_nand_offset, &bmp_header_size,
-			NULL, nand_info[nand_curr_device].size,
-			(u_char *)bmp_load_addr);
-	if (res < 0)
-		return res;
-
-	bmp_hdr = (struct bmp_header *)bmp_load_addr;
-	bmp_size = le32_to_cpu(bmp_hdr->file_size);
-
-	if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
-		goto splash_address_too_high;
-
-	return nand_read_skip_bad(&nand_info[nand_curr_device],
-			splash_screen_nand_offset, &bmp_size,
-			NULL, nand_info[nand_curr_device].size,
-			(u_char *)bmp_load_addr);
-
-splash_address_too_high:
-	printf("Error: splashimage address too high. Data overwrites U-Boot "
-		"and/or placed beyond DRAM boundaries.\n");
-
-	return -1;
-}
-#else
-static inline int splash_load_from_nand(void)
-{
-	return -1;
-}
-#endif /* CONFIG_CMD_NAND */
-
 #ifdef CONFIG_SPL_BUILD
 /*
  * Routine: get_board_mem_timings
@@ -111,25 +59,13 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 }
 #endif
 
+#define CM_T35_SPLASH_NAND_OFFSET 0x100000
+
 int splash_screen_prepare(void)
 {
-	char *env_splashimage_value;
+	return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
-	u32 bmp_load_addr;
-
-	env_splashimage_value = getenv("splashimage");
-	if (env_splashimage_value == NULL)
-		return -1;
-
-	bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
-	if (bmp_load_addr == 0) {
-		printf("Error: bad splashimage address specified\n");
-		return -1;
 }
 
-	return splash_load_from_nand(bmp_load_addr);
-}
-#endif /* CONFIG_LCD */
-
 /*
  * Routine: board_init
  * Description: hardware init.
@@ -154,34 +90,18 @@ int board_init(void)
 	return 0;
 }
 
-static u32 cm_t3x_rev;
-
 /*
  * Routine: get_board_rev
  * Description: read system revision
  */
 u32 get_board_rev(void)
 {
-	if (!cm_t3x_rev)
+	return cl_eeprom_get_board_rev();
-		cm_t3x_rev = cl_eeprom_get_board_rev();
-
-	return cm_t3x_rev;
 };
 
-/*
- * Routine: misc_init_r
- * Description: display die ID
- */
 int misc_init_r(void)
 {
-	u32 board_rev = get_board_rev();
+	cl_print_pcb_info();
-	u32 rev_major = board_rev / 100;
-	u32 rev_minor = board_rev - (rev_major * 100);
-
-	if ((rev_minor / 10) * 10 == rev_minor)
-		rev_minor = rev_minor / 10;
-
-	printf("PCB:   %u.%u\n", rev_major, rev_minor);
 	dieid_num_r();
 
 	return 0;
@@ -462,37 +382,12 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-/*
- * Routine: setup_net_chip_gmpc
- * Description: Setting up the configuration GPMC registers specific to the
- *		Ethernet hardware.
- */
-static void setup_net_chip_gmpc(void)
-{
-	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
-	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
-			      CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
-	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
-			      SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
-
-	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
-	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-
-	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-
-	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
-		&ctrl_base->gpmc_nadv_ale);
-}
-
 #ifdef CONFIG_SYS_I2C_OMAP34XX
 /*
  * Routine: reset_net_chip
  * Description: reset the Ethernet controller via TPS65930 GPIO
  */
-static void reset_net_chip(void)
+static int cm_t3x_reset_net_chip(int gpio)
 {
 	/* Set GPIO1 of TPS65930 as output */
 	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
@@ -507,9 +402,10 @@ static void reset_net_chip(void)
 	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
 			     0x02);
 	mdelay(1);
+	return 0;
 }
 #else
-static inline void reset_net_chip(void) {}
+static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
 #endif
 
 #ifdef CONFIG_SMC911X
@@ -536,7 +432,6 @@ static int handle_mac_address(void)
 	return eth_setenv_enetaddr("ethaddr", enetaddr);
 }
 
-
 /*
  * Routine: board_eth_init
  * Description: initialize module and base-board Ethernet chips
@@ -545,18 +440,16 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0, rc1 = 0;
 
-	setup_net_chip_gmpc();
-	reset_net_chip();
-
 	rc1 = handle_mac_address();
 	if (rc1)
 		printf("No MAC address found! ");
 
-	rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
+	rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
+				    cm_t3x_reset_net_chip, -EINVAL);
 	if (rc1 > 0)
 		rc++;
 
-	rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+	rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
 	if (rc1 > 0)
 		rc++;
 
@@ -564,16 +457,6 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-void __weak get_board_serial(struct tag_serialnr *serialnr)
-{
-	/*
-	 * This corresponds to what happens when we can communicate with the
-	 * eeprom but don't get a valid board serial value.
-	 */
-	serialnr->low = 0;
-	serialnr->high = 0;
-};
-
 #ifdef CONFIG_USB_EHCI_OMAP
 struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
@@ -588,16 +471,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 	u8 val;
 	int offset;
 
-	if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
+	cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
-		printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
-				SB_T35_USB_HUB_RESET_GPIO);
-		return -1;
-	}
-
-	gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
-	udelay(10);
-	gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
-	udelay(1000);
 
 	offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
 	twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
@@ -614,6 +488,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 int ehci_hcd_stop(void)
 {
+	cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
 	return omap_ehci_hcd_stop();
 }
 #endif /* CONFIG_USB_EHCI_OMAP */

board/compulab/cm_t3517/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_CM_T3517
+
+config SYS_BOARD
+	default "cm_t3517"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_CONFIG_NAME
+	default "cm_t3517"
+
+endif

board/compulab/cm_t3517/MAINTAINERS

@@ -0,0 +1,6 @@
+CM_T3517 BOARD
+M:	Igor Grinberg <grinberg@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cm_t3517/
+F:	include/configs/cm_t3517.h
+F:	configs/cm_t3517_defconfig

board/compulab/cm_t3517/Makefile

@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= cm_t3517.o mux.o

board/compulab/cm_t3517/cm_t3517.c

@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <mmc.h>
+#include <linux/compiler.h>
+#include <linux/usb/musb.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/am35x_def.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/ehci-omap.h>
+
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"CM-T3517 board",
+	"NAND 128/512M",
+};
+
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config cm_t3517_musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+static struct omap_musb_board_data cm_t3517_musb_board_data = {
+	.set_phy_power		= am35x_musb_phy_power,
+	.clear_irq		= am35x_musb_clear_irq,
+	.reset			= am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
+#if defined(CONFIG_MUSB_HOST)
+	.mode           = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+	.mode		= MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+	.config         = &cm_t3517_musb_config,
+	.power          = 250,
+	.platform_ops	= &am35x_ops,
+	.board_data	= &cm_t3517_musb_board_data,
+};
+
+static void cm_t3517_musb_init(void)
+{
+	/*
+	 * Set up USB clock/mode in the DEVCONF2 register.
+	 * USB2.0 PHY reference clock is 13 MHz
+	 */
+	clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+			CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+			CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+			CONF2_VBDTCTEN | CONF2_DATPOL);
+
+	if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
+			  (void *)AM35XX_IPSS_USBOTGSS_BASE))
+		printf("Failed initializing AM35x MUSB!\n");
+}
+#else
+static inline void am3517_evm_musb_init(void) {}
+#endif
+
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+	cm_t3517_musb_init();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	cl_print_pcb_info();
+	dieid_num_r();
+
+	return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_CD_GPIO 144
+#define SB_T35_WP_GPIO 59
+
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONTROL_EFUSE_EMAC_LSB  0x48002380
+#define CONTROL_EFUSE_EMAC_MSB  0x48002384
+
+static int am3517_get_efuse_enetaddr(u8 *enetaddr)
+{
+	u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
+	u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
+
+	enetaddr[0] = (u8)((msb >> 16) & 0xff);
+	enetaddr[1] = (u8)((msb >> 8)  & 0xff);
+	enetaddr[2] = (u8)(msb & 0xff);
+	enetaddr[3] = (u8)((lsb >> 16) & 0xff);
+	enetaddr[4] = (u8)((lsb >> 8)  & 0xff);
+	enetaddr[5] = (u8)(lsb & 0xff);
+
+	return is_valid_ether_addr(enetaddr);
+}
+
+static inline int cm_t3517_init_emac(bd_t *bis)
+{
+	int ret = cpu_eth_init(bis);
+
+	if (ret > 0)
+		return ret;
+
+	printf("Failed initializing EMAC! ");
+	return 0;
+}
+#else /* !CONFIG_DRIVER_TI_EMAC */
+static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
+static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int cm_t3517_handle_mac_address(void)
+{
+	unsigned char enetaddr[6];
+	int ret;
+
+	ret = eth_getenv_enetaddr("ethaddr", enetaddr);
+	if (ret)
+		return 0;
+
+	ret = cl_eeprom_read_mac_addr(enetaddr);
+	if (ret) {
+		ret = am3517_get_efuse_enetaddr(enetaddr);
+		if (ret)
+			return ret;
+	}
+
+	if (!is_valid_ether_addr(enetaddr))
+		return -1;
+
+	return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define SB_T35_ETH_RST_GPIO 164
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0, rc1 = 0;
+
+	rc1 = cm_t3517_handle_mac_address();
+	if (rc1)
+		printf("No MAC address found! ");
+
+	rc1 = cm_t3517_init_emac(bis);
+	if (rc1 > 0)
+		rc++;
+
+	rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
+				    NULL, SB_T35_ETH_RST_GPIO);
+	if (rc1 > 0)
+		rc++;
+
+	return rc;
+}
+
+#ifdef CONFIG_USB_EHCI_OMAP
+static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
+	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define CM_T3517_USB_HUB_RESET_GPIO	152
+#define SB_T35_USB_HUB_RESET_GPIO	98
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+			struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
+	cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
+
+	return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+	cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
+	cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
+
+	return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_OMAP */

board/compulab/cm_t3517/mux.c

@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+void set_muxconf_regs(void)
+{
+	/* SDRC */
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7));
+
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
+
+	/* SB-T35 Ethernet */
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0));
+	/* DVI enable */
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | DIS  | M4));/*GPIO_54*/
+	/* DataImage backlight */
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | DIS  | M4));/*GPIO_58*/
+
+	/* SB-T35 SD/MMC WP GPIO59 */
+	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTU | EN  | M4)); /*GPIO_59*/
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0));
+	/* SB-T35 Audio Enable GPIO61 */
+	MUX_VAL(CP(GPMC_NBE1),		(IDIS | PTU | EN  | M4)); /*GPIO_61*/
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
+	/* SB-T35 Ethernet IRQ GPIO65 */
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)); /*GPIO_65*/
+
+	/* UART3 Console */
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0));
+	/* RTC V3020 nCS GPIO163 */
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | EN  | M4)); /*GPIO_163*/
+	/* SB-T35 Ethernet nRESET GPIO164 */
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTU | EN  | M4)); /*GPIO_164*/
+
+	/* SB-T35 SD/MMC CD GPIO144 */
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M4)); /*GPIO_144*/
+	/* WIFI nRESET GPIO145 */
+	MUX_VAL(CP(UART2_RTS),		(IEN  | PTD | EN  | M4)); /*GPIO_145*/
+	/* USB1 PHY Reset GPIO 146 */
+	MUX_VAL(CP(UART2_TX),		(IEN  | PTD | EN  | M4)); /*GPIO_146*/
+	/* USB2 PHY Reset GPIO 147 */
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | EN  | M4)); /*GPIO_147*/
+
+	/* MMC1 */
+	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0));
+
+	/* DSS */
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0));
+
+	/* I2C */
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0));
+
+	/* SB-T35 USB HUB Reset GPIO98 */
+	MUX_VAL(CP(CCDC_WEN),		(IDIS | PTU | EN  | M4)); /*GPIO_98*/
+	/* CM-T3517 USB HUB Reset GPIO152 */
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)); /*GPIO_152*/
+
+	/* RMII */
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0));
+	MUX_VAL(CP(RMII_RXD0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_RXER),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(RMII_TXD0),		(IDIS | M0));
+	MUX_VAL(CP(RMII_TXD1),		(IDIS | M0));
+	MUX_VAL(CP(RMII_TXEN),		(IDIS | M0));
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTU | DIS | M0));
+
+	/* Green LED GPIO186 */
+	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*GPIO_186*/
+
+	/* SPI */
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+	MUX_VAL(CP(MCBSP1_DX),		(IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+	MUX_VAL(CP(MCBSP1_DR),		(IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN | PTU | EN  | M1)); /*MCSPI4_CS0*/
+	/* LCD reset GPIO157 */
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | DIS | M4)); /*GPIO_157*/
+
+	/* RTC V3020 CS Enable GPIO160 */
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTD | EN  | M4)); /*GPIO_160*/
+	/* SB-T35 LVDS Transmitter SHDN GPIO162 */
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTU | DIS | M4)); /*GPIO_162*/
+
+	/* USB0 - mUSB */
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0));
+	/* USB1 EHCI */
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT0*/
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT1*/
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT2*/
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT3*/
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT4*/
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT5*/
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT6*/
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DT7*/
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_DIR*/
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M3)); /*HSUSB1_NXT*/
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+	/* USB2 EHCI */
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT0*/
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT1*/
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT2*/
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT3*/
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT4*/
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DT5*/
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT6*/
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M3)); /*HSUSB2_DT7*/
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_DIR*/
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | EN  | M3)); /*HSUSB2_NXT*/
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+	/* SYS_BOOT */
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTU | DIS | M4)); /*GPIO_2*/
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTU | DIS | M4)); /*GPIO_3*/
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTU | DIS | M4)); /*GPIO_4*/
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTU | DIS | M4)); /*GPIO_5*/
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTU | DIS | M4)); /*GPIO_6*/
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTU | DIS | M4)); /*GPIO_7*/
+}

board/compulab/cm_t54/cm_t54.c

@@ -100,16 +100,11 @@ uint mmc_get_env_part(struct mmc *mmc)
 #define SB_T54_CD_GPIO 228
 #define SB_T54_WP_GPIO 229
 
-int board_mmc_getcd(struct mmc *mmc)
-{
-	return !gpio_get_value(SB_T54_CD_GPIO);
-}
-
 int board_mmc_init(bd_t *bis)
 {
 	int ret0, ret1;
 
-	ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO);
+	ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
 	if (ret0)
 		printf("cm_t54: failed to initialize mmc0\n");
 

board/compulab/common/Makefile

@@ -6,5 +6,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-y				+= common.o
 obj-$(CONFIG_SYS_I2C)		+= eeprom.o
 obj-$(CONFIG_LCD)		+= omap3_display.o
+obj-$(CONFIG_SPLASH_SCREEN)	+= splash.o
+obj-$(CONFIG_SMC911X)		+= omap3_smc911x.o

board/compulab/common/common.c

@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+#include "eeprom.h"
+
+void cl_print_pcb_info(void)
+{
+	u32 board_rev = get_board_rev();
+	u32 rev_major = board_rev / 100;
+	u32 rev_minor = board_rev - (rev_major * 100);
+
+	if ((rev_minor / 10) * 10 == rev_minor)
+		rev_minor = rev_minor / 10;
+
+	printf("PCB:   %u.%u\n", rev_major, rev_minor);
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void __weak get_board_serial(struct tag_serialnr *serialnr)
+{
+	/*
+	 * This corresponds to what happens when we can communicate with the
+	 * eeprom but don't get a valid board serial value.
+	 */
+	serialnr->low = 0;
+	serialnr->high = 0;
+};
+#endif
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label)
+{
+	if (gpio_request(gpio, label)) {
+		printf("Error: can't obtain GPIO%d for %s", gpio, label);
+		return -1;
+	}
+
+	gpio_direction_output(gpio, 0);
+	udelay(10);
+	gpio_set_value(gpio, 1);
+	udelay(1000);
+	return 0;
+}
+
+void cl_usb_hub_deinit(int gpio)
+{
+	gpio_free(gpio);
+}
+#endif

board/compulab/common/common.h

@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CL_COMMON_
+#define _CL_COMMON_
+
+#include <asm/errno.h>
+
+void cl_print_pcb_info(void);
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label);
+void cl_usb_hub_deinit(int gpio);
+#else /* !CONFIG_CMD_USB */
+static inline int cl_usb_hub_init(int gpio, const char *label)
+{
+	return -ENOSYS;
+}
+static inline void cl_usb_hub_deinit(int gpio) {}
+#endif /* CONFIG_CMD_USB */
+
+#ifdef CONFIG_SPLASH_SCREEN
+int cl_splash_screen_prepare(int nand_offset);
+#else /* !CONFIG_SPLASH_SCREEN */
+static inline int cl_splash_screen_prepare(int nand_offset)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#ifdef CONFIG_SMC911X
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+			  int (*reset)(int), int rst_gpio);
+#else /* !CONFIG_SMC911X */
+static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+					int (*reset)(int), int rst_gpio)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_SMC911X */
+
+#endif /* _CL_COMMON_ */

board/compulab/common/eeprom.c

@@ -109,23 +109,27 @@ int cl_eeprom_read_mac_addr(uchar *buf)
 	return cl_eeprom_read(offset, buf, 6);
 }
 
+static u32 board_rev;
+
 /*
  * Routine: cl_eeprom_get_board_rev
  * Description: read system revision from eeprom
  */
 u32 cl_eeprom_get_board_rev(void)
 {
-	u32 rev = 0;
 	char str[5]; /* Legacy representation can contain at most 4 digits */
 	uint offset = BOARD_REV_OFFSET_LEGACY;
 
+	if (board_rev)
+		return board_rev;
+
 	if (cl_eeprom_setup_layout())
 		return 0;
 
 	if (cl_eeprom_layout != LAYOUT_LEGACY)
 		offset = BOARD_REV_OFFSET;
 
-	if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
+	if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
 		return 0;
 
 	/*
@@ -133,9 +137,9 @@ u32 cl_eeprom_get_board_rev(void)
 	 * representation. i.e. for rev 1.00: 0x100 --> 0x64
 	 */
 	if (cl_eeprom_layout == LAYOUT_LEGACY) {
-		sprintf(str, "%x", rev);
+		sprintf(str, "%x", board_rev);
-		rev = simple_strtoul(str, NULL, 10);
+		board_rev = simple_strtoul(str, NULL, 10);
 	}
 
-	return rev;
+	return board_rev;
 };

board/compulab/common/omap3_smc911x.c

@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+
+static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = {
+	NET_GPMC_CONFIG1,
+	NET_GPMC_CONFIG2,
+	NET_GPMC_CONFIG3,
+	NET_GPMC_CONFIG4,
+	NET_GPMC_CONFIG5,
+	NET_GPMC_CONFIG6,
+	0
+};
+
+static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config,
+			      &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+	       &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_OMAP_GPIO
+static int cl_omap3_smc911x_reset_net_chip(int gpio)
+{
+	int err;
+
+	if (!gpio_is_valid(gpio))
+		return -EINVAL;
+
+	err = gpio_request(gpio, "eth rst");
+	if (err)
+		return err;
+
+	/* Set gpio as output and send a pulse */
+	gpio_direction_output(gpio, 1);
+	udelay(1);
+	gpio_set_value(gpio, 0);
+	mdelay(40);
+	gpio_set_value(gpio, 1);
+	mdelay(1);
+
+	return 0;
+}
+#else /* !CONFIG_OMAP_GPIO */
+static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; }
+#endif /* CONFIG_OMAP_GPIO */
+
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+			  int (*reset)(int), int rst_gpio)
+{
+	int ret;
+
+	cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
+
+	if (reset)
+		reset(rst_gpio);
+	else
+		cl_omap3_smc911x_reset_net_chip(rst_gpio);
+
+	ret = smc911x_initialize(id, base_addr);
+	if (ret > 0)
+		return ret;
+
+	printf("Failed initializing SMC911x! ");
+	return 0;
+}

board/compulab/common/splash.c

@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <bmp_layout.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+	struct bmp_header *bmp_hdr;
+	int res;
+	size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
+
+	if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
+		goto splash_address_too_high;
+
+	res = nand_read_skip_bad(&nand_info[nand_curr_device],
+			nand_offset, &bmp_header_size,
+			NULL, nand_info[nand_curr_device].size,
+			(u_char *)bmp_load_addr);
+	if (res < 0)
+		return res;
+
+	bmp_hdr = (struct bmp_header *)bmp_load_addr;
+	bmp_size = le32_to_cpu(bmp_hdr->file_size);
+
+	if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
+		goto splash_address_too_high;
+
+	return nand_read_skip_bad(&nand_info[nand_curr_device],
+			nand_offset, &bmp_size,
+			NULL, nand_info[nand_curr_device].size,
+			(u_char *)bmp_load_addr);
+
+splash_address_too_high:
+	printf("Error: splashimage address too high. Data overwrites U-Boot "
+		"and/or placed beyond DRAM boundaries.\n");
+
+	return -1;
+}
+#else
+static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+	return -1;
+}
+#endif /* CONFIG_CMD_NAND */
+
+int cl_splash_screen_prepare(int nand_offset)
+{
+	char *env_splashimage_value;
+	u32 bmp_load_addr;
+
+	env_splashimage_value = getenv("splashimage");
+	if (env_splashimage_value == NULL)
+		return -1;
+
+	bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
+	if (bmp_load_addr == 0) {
+		printf("Error: bad splashimage address specified\n");
+		return -1;
+	}
+
+	return splash_load_from_nand(bmp_load_addr, nand_offset);
+}

board/siemens/pxm2/board.c

@@ -229,7 +229,7 @@ int board_eth_init(bd_t *bis)
 #endif /* #ifdef CONFIG_FACTORYSET */
 
 	/* Set rgmii mode and enable rmii clock to be sourced from chip */
-	writel(RGMII_MODE_ENABLE , &cdev->miisel);
+	writel(RGMII_MODE_ENABLE  | RGMII_INT_DELAY, &cdev->miisel);
 
 	rv = cpsw_register(&cpsw_data);
 	if (rv < 0)

board/ti/am335x/Kconfig

@@ -22,4 +22,19 @@ config CONS_INDEX
 	  board you may want something other than UART0 as for example the IDK
 	  uses UART3 so enter 4 here.
 
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The AM335x SoC supports having a NOR flash connected to the GPMC.
+	  In practice this is seen as a NOR flash module connected to the
+	  "memory cape" for the BeagleBone family.
+
+config NOR_BOOT
+	bool "Support for booting from NOR flash"
+	depends on NOR
+	help
+	  Enabling this will make a U-Boot binary that is capable of being
+	  booted via NOR.  In this case we will enable certain pinmux early
+	  as the ROM only partially sets up pinmux.  We also default to using
+	  NOR for environment.
 endif

board/ti/ks2_evm/README

@@ -3,10 +3,11 @@ U-Boot port for Texas Instruments Keystone II EVM boards
 
 Author: Murali Karicheri <m-karicheri2@ti.com>
 
-This README has information on the u-boot port for K2HK, K2E boards.
+This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards.
 Documentation for this board can be found at
 http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
 https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
+https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
 
 The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
 More details on these SoCs are available at company websites
@@ -14,7 +15,10 @@ More details on these SoCs are available at company websites
  K2H: http://www.ti.com/product/tci6638k2h
 
 The K2E SoC details are available at
- K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+ http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+
+The K2L SoC details are available at
+ http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
 
 Board configuration:
 ====================
@@ -25,6 +29,7 @@ Some of the peripherals that are configured by u-boot
 +------+-------+-------+-----------+-----------+-------+-------+----+
 |K2HK  |2      |512MB  |6MB	   |4(2)       |2      |3      |3   |
 |K2E   |4      |512MB  |2MB	   |8(2)       |2      |3      |3   |
+|K2L   |2      |512MB  |2MB	   |4(2)       |4      |3      |3   |
 +------+-------+-------+-----------+-----------+-------+-------+----+
 
 There are only 2 eth port installed on the boards.
@@ -41,10 +46,13 @@ The port related files can be found at following folders
 Board configuration files:
 include/configs/k2hk_evm.h
 include/configs/k2e_evm.h
+include/configs/k2l_evm.h
+include/configs/k2l_evm.h
 
 As u-boot is migrating to Kconfig there is also board defconfig files
 configs/k2e_evm_defconfig
 configs/k2hk_evm_defconfig
+configs/k2l_evm_defconfig
 
 Supported boot modes:
  - SPI NOR boot
@@ -58,7 +66,7 @@ Supported image formats:
 
 Build instructions:
 ===================
-Examples for k2hk, for k2e just replace k2hk prefix accordingly.
+Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly.
 Don't forget to add ARCH=arm and CROSS_COMPILE.
 
 To build u-boot.bin
@@ -84,6 +92,8 @@ Use u-boot.bin from the build folder for loading and running u-boot binary
 on EVM. Follow instructions at
 K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
 K2E  http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
+K2L  http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
+
 to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
 and Power ON the EVM.  Follow instructions to connect serial port of EVM to
 PC and start TeraTerm or Hyper Terminal.
@@ -128,8 +138,8 @@ instructions:
 2. Suspend Target. Select Run -> Suspend from top level menu
    CortexA15_1 (Free Running)"
 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
-   through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM
+   through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
-   using CCS", but using address 0x87000000.
+   EVM using CCS", but using address 0x87000000.
 4. Free Run the target as described earlier (step 4) to get u-boot prompt
 5. At the U-Boot console type following to setup u-boot environment variables.
    setenv addr_uboot 0x87000000

board/ti/ks2_evm/board.c

@@ -122,7 +122,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 	int nbanks;
 	u64 size[2];
 	u64 start[2];
-	char name[32];
 	int nodeoffset;
 	u32 ddr3a_size;
 	int unitrd_fixup = 0;
@@ -158,15 +157,13 @@ void ft_board_setup(void *blob, bd_t *bd)
 	}
 
 	/* reserve memory at start of bank */
-	sprintf(name, "mem_reserve_head");
+	env = getenv("mem_reserve_head");
-	env = getenv(name);
 	if (env) {
 		start[0] += ustrtoul(env, &endp, 0);
 		size[0] -= ustrtoul(env, &endp, 0);
 	}
 
-	sprintf(name, "mem_reserve");
+	env = getenv("mem_reserve");
-	env = getenv(name);
 	if (env)
 		size[0] -= ustrtoul(env, &endp, 0);
 

board/ti/ks2_evm/board_k2l.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/hardware.h>
-#include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -42,6 +42,44 @@ static struct pll_init_data tetris_pll_config[] = {
 static struct pll_init_data pa_pll_config =
 	PASS_PLL_983;
 
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+	{
+		.int_name        = "K2L_EMAC",
+		.rx_flow         = 0,
+		.phy_addr        = 0,
+		.slave_port      = 1,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name        = "K2L_EMAC1",
+		.rx_flow         = 8,
+		.phy_addr        = 1,
+		.slave_port      = 2,
+		.sgmii_link_type = SGMII_LINK_MAC_PHY,
+	},
+	{
+		.int_name        = "K2L_EMAC2",
+		.rx_flow         = 16,
+		.phy_addr        = 2,
+		.slave_port      = 3,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+	{
+		.int_name        = "K2L_EMAC3",
+		.rx_flow         = 32,
+		.phy_addr        = 3,
+		.slave_port      = 4,
+		.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+	},
+};
+
+int get_num_eth_ports(void)
+{
+	return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {

configs/am335x_evm_nor_defconfig

@@ -1,5 +1,6 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND,NOR"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
 CONFIG_CONS_INDEX=1
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_NOR=y

configs/am335x_evm_norboot_defconfig

@@ -1,4 +1,5 @@
-CONFIG_SYS_EXTRA_OPTIONS="NOR,NOR_BOOT"
 CONFIG_CONS_INDEX=1
 CONFIG_ARM=y
 CONFIG_TARGET_AM335X_EVM=y
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y

configs/cm_t3517_defconfig

@@ -0,0 +1,4 @@
+CONFIG_SPL=n
++S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
++S:CONFIG_TARGET_CM_T3517=y

drivers/dma/keystone_nav.c

@@ -81,9 +81,6 @@ void qm_close(void)
 {
 	u32	j;
 
-	if (qm_cfg == NULL)
-		return;
-
 	queue_close(qm_cfg->qpool_num);
 
 	qm_cfg->mngr_cfg->link_ram_base0	= 0;
@@ -105,9 +102,6 @@ void qm_push(struct qm_host_desc *hd, u32 qnum)
 {
 	u32 regd;
 
-	if (!qm_cfg)
-		return;
-
 	cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
 	regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
 	writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
@@ -127,9 +121,6 @@ struct qm_host_desc *qm_pop(u32 qnum)
 {
 	u32 uhd;
 
-	if (!qm_cfg)
-		return NULL;
-
 	uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
 	if (uhd)
 		cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
@@ -139,9 +130,6 @@ struct qm_host_desc *qm_pop(u32 qnum)
 
 struct qm_host_desc *qm_pop_from_free_pool(void)
 {
-	if (!qm_cfg)
-		return NULL;
-
 	return qm_pop(qm_cfg->qpool_num);
 }
 

drivers/mmc/omap_hsmmc.c

@@ -611,7 +611,8 @@ static int omap_hsmmc_getcd(struct mmc *mmc)
 	if (cd_gpio < 0)
 		return 1;
 
-	return gpio_get_value(cd_gpio);
+	/* NOTE: assumes card detect signal is active-low */
+	return !gpio_get_value(cd_gpio);
 }
 
 static int omap_hsmmc_getwp(struct mmc *mmc)
@@ -624,6 +625,7 @@ static int omap_hsmmc_getwp(struct mmc *mmc)
 	if (wp_gpio < 0)
 		return 0;
 
+	/* NOTE: assumes write protect signal is active-high */
 	return gpio_get_value(wp_gpio);
 }
 #endif

drivers/net/keystone_net.c

@@ -315,7 +315,7 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
 	writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
 	writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
 
-#ifdef CONFIG_K2E_EVM
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 	/* Map RX packet flow priority to 0 */
 	writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
 #endif
@@ -400,6 +400,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 
 	keystone2_net_serdes_setup();
 
+	if (sys_has_mdio)
+		keystone2_mdio_reset(mdio_bus);
+
 	keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
 			      eth_priv->sgmii_link_type);
 
@@ -582,7 +585,7 @@ static void keystone2_net_serdes_setup(void)
 			&ks2_serdes_sgmii_156p25mhz,
 			CONFIG_KSNET_SERDES_LANES_PER_SGMII);
 
-#ifdef CONFIG_SOC_K2E
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
 			&ks2_serdes_sgmii_156p25mhz,
 			CONFIG_KSNET_SERDES_LANES_PER_SGMII);

drivers/net/phy/marvell.c

@@ -276,6 +276,57 @@ static int m88e1111s_config(struct phy_device *phydev)
 	return 0;
 }
 
+/**
+ * m88e1518_phy_writebits - write bits to a register
+ */
+void m88e1518_phy_writebits(struct phy_device *phydev,
+		   u8 reg_num, u16 offset, u16 len, u16 data)
+{
+	u16 reg, mask;
+
+	if ((len + offset) >= 16)
+		mask = 0 - (1 << offset);
+	else
+		mask = (1 << (len + offset)) - (1 << offset);
+
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
+
+	reg &= ~mask;
+	reg |= data << offset;
+
+	phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
+}
+
+static int m88e1518_config(struct phy_device *phydev)
+{
+	/*
+	 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
+	 * /88E1514 Rev A0, Errata Section 3.1
+	 */
+	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);	/* page 0xff */
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);	/* reg page 0 */
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);    /* reg page 18 */
+		/* Write HWCFG_MODE = SGMII to Copper */
+		m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
+
+		/* Phy reset */
+		m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);     /* reg page 18 */
+		udelay(100);
+	}
+
+	return m88e1111s_config(phydev);
+}
+
 /* Marvell 88E1118 */
 static int m88e1118_config(struct phy_device *phydev)
 {
@@ -493,7 +544,7 @@ static struct phy_driver M88E1518_driver = {
 	.uid = 0x1410dd1,
 	.mask = 0xffffff0,
 	.features = PHY_GBIT_FEATURES,
-	.config = &m88e1111s_config,
+	.config = &m88e1518_config,
 	.startup = &m88e1011s_startup,
 	.shutdown = &genphy_shutdown,
 };

include/configs/am335x_evm.h

@@ -314,6 +314,18 @@
 #define CONFIG_AM335X_USB1
 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
 
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE	0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+#endif
+
 #ifdef CONFIG_MUSB_HOST
 #define CONFIG_CMD_USB
 #define CONFIG_USB_STORAGE
@@ -325,8 +337,8 @@
 #define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
 
 /* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
 #endif /* CONFIG_MUSB_GADGET */
 

include/configs/cm_t3517.h

@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2013 CompuLab, Ltd.
+ * Author: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * Configuration settings for the CompuLab CM-T3517 board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP	/* in a TI OMAP core */
+#define CONFIG_CM_T3517	/* working with CM-T3517 */
+#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_TEXT_BASE	0x80008000
+
+/*
+ * This is needed for the DMA stuff.
+ * Although the default iss 64, we still define it
+ * to be on the safe side once the default is changed.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+/*
+ * The early kernel mapping on ARM currently only maps from the base of DRAM
+ * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
+ * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
+ * so that leaves DRAM base to DRAM base + 0x4000 available.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	        0x4000
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+#define CONFIG_OMAP_GPIO
+
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_MUSB_AM35X
+
+#ifndef CONFIG_USB_MUSB_AM35X
+#define CONFIG_USB_OMAP3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
+#else /* !CONFIG_USB_MUSB_AM35X */
+#define CONFIG_MUSB_HOST
+#define CONFIG_MUSB_PIO_ONLY
+#endif /* CONFIG_USB_MUSB_AM35X */
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=nand"
+#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
+				"1920k(u-boot),256k(u-boot-env),"\
+				"4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_GPIO
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"baudrate=115200\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=auto\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcrootfstype=ext4\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 2a0000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"CM-T3517 # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* CM-T3517 DRAM is only on CS0 */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define CONFIG_SYS_CS0_SIZE		(256 << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE	(0x2C000000 + (16 << 20))
+#endif /* CONFIG_CMD_NET */
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
+					 CONFIG_SYS_INIT_RAM_SIZE -	\
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Status LED */
+#define CONFIG_STATUS_LED		/* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO			186 /* CM-T3517 Green LED is GPIO186 */
+#define GREEN_LED_DEV			0
+#define STATUS_LED_BIT			GREEN_LED_GPIO
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT			GREEN_LED_DEV
+
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_6	/* GPIO186 is in GPIO bank 6  */
+#endif
+
+/* Display Configuration */
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_VIDEO_OMAP3
+#define LCD_BPP		LCD_COLOR16
+
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASHIMAGE_GUARD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */

include/configs/k2e_evm.h

@@ -17,14 +17,15 @@
 /* U-Boot general configuration */
 #define CONFIG_SYS_PROMPT               "K2E EVM # "
 
-#define KS2_ARGS_UBI   "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
-		       "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
+	"addr_mon=0x0c140000\0"						\
-
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-#define KS2_FDT_NAME   "name_fdt=k2e-evm.dtb\0"
+	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"		\
-#define KS2_ADDR_MON   "addr_mon=0x0c140000\0"
+	"name_fdt=uImage-k2e-evm.dtb\0"					\
-#define KS2_NAME_MON   "name_mon=skern-k2e-evm.bin\0"
+	"name_mon=skern-k2e-evm.bin\0"					\
-#define NAME_UBOOT     "name_uboot=u-boot-spi-k2e-evm.gph\0"
+	"name_ubi=k2e-evm-ubifs.ubi\0"					\
-#define NAME_UBI       "name_ubi=k2e-evm-ubifs.ubi\0"
+	"name_uboot=u-boot-spi-k2e-evm.gph\0"				\
+	"name_fs=arago-console-image-k2e-evm.cpio.gz\0"
 
 #include <configs/ks2_evm.h>
 
@@ -35,14 +36,8 @@
 #define CONFIG_SYS_NAND_PAGE_2K
 
 /* Network */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_TI_KSNAV
-#define CONFIG_KSNAV_PKTDMA_NETCP
 #define CONFIG_KSNET_NETCP_V1_5
 #define CONFIG_KSNET_CPSW_NUM_PORTS	9
 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 
-/* SerDes */
-#define CONFIG_TI_KEYSTONE_SERDES
-
 #endif /* __CONFIG_K2E_EVM_H */

include/configs/k2hk_evm.h

@@ -17,14 +17,15 @@
 /* U-Boot general configuration */
 #define CONFIG_SYS_PROMPT               "K2HK EVM # "
 
-#define KS2_ARGS_UBI   "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
-		       "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
+	"addr_mon=0x0c5f0000\0"						\
-
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-#define KS2_FDT_NAME   "name_fdt=k2hk-evm.dtb\0"
+	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"		\
-#define KS2_ADDR_MON   "addr_mon=0x0c5f0000\0"
+	"name_fdt=uImage-k2hk-evm.dtb\0"				\
-#define KS2_NAME_MON   "name_mon=skern-k2hk-evm.bin\0"
+	"name_mon=skern-k2hk-evm.bin\0"					\
-#define NAME_UBOOT     "name_uboot=u-boot-spi-k2hk-evm.gph\0"
+	"name_ubi=k2hk-evm-ubifs.ubi\0"					\
-#define NAME_UBI       "name_ubi=k2hk-evm-ubifs.ubi\0"
+	"name_uboot=u-boot-spi-k2hk-evm.gph\0"				\
+	"name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
 
 #include <configs/ks2_evm.h>
 
@@ -35,13 +36,7 @@
 #define CONFIG_SYS_NAND_PAGE_2K
 
 /* Network */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_TI_KSNAV
-#define CONFIG_KSNAV_PKTDMA_NETCP
 #define CONFIG_KSNET_NETCP_V1_0
 #define CONFIG_KSNET_CPSW_NUM_PORTS	5
 
-/* SerDes */
-#define CONFIG_TI_KEYSTONE_SERDES
-
 #endif /* __CONFIG_K2HK_EVM_H */

include/configs/k2l_evm.h

@@ -17,14 +17,15 @@
 /* U-Boot general configuration */
 #define CONFIG_SYS_PROMPT		"K2L EVM # "
 
-#define KS2_ARGS_UBI   "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
-		       "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0"
+	"addr_mon=0x0c140000\0"						\
-
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
-#define KS2_FDT_NAME	"name_fdt=k2l-evm.dtb\0"
+	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0"		\
-#define KS2_ADDR_MON	"addr_mon=0x0c140000\0"
+	"name_fdt=uImage-k2l-evm.dtb\0"					\
-#define KS2_NAME_MON	"name_mon=skern-k2l-evm.bin\0"
+	"name_mon=skern-k2l-evm.bin\0"					\
-#define NAME_UBOOT	"name_uboot=u-boot-spi-k2l-evm.gph\0"
+	"name_ubi=k2l-evm-ubifs.ubi\0"					\
-#define NAME_UBI	"name_ubi=k2l-evm-ubifs.ubi\0"
+	"name_uboot=u-boot-spi-k2l-evm.gph\0"				\
+	"name_fs=arago-console-image-k2l-evm.cpio.gz\0"
 
 #include <configs/ks2_evm.h>
 
@@ -34,4 +35,9 @@
 /* NAND Configuration */
 #define CONFIG_SYS_NAND_PAGE_4K
 
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS	5
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
 #endif /* __CONFIG_K2L_EVM_H */

include/configs/ks2_evm.h

@@ -105,6 +105,7 @@
 #define CONFIG_SYS_SGMII_RATESCALE	2
 
 /* Keyston Navigator Configuration */
+#define CONFIG_TI_KSNAV
 #define CONFIG_KSNAV_QM_BASE_ADDRESS		KS2_QM_BASE_ADDRESS
 #define CONFIG_KSNAV_QM_CONF_BASE		KS2_QM_CONF_BASE
 #define CONFIG_KSNAV_QM_DESC_SETUP_BASE		KS2_QM_DESC_SETUP_BASE
@@ -121,6 +122,7 @@
 #define CONFIG_KSNAV_QM_QPOOL_NUM		KS2_QM_QPOOL_NUM
 
 /* NETCP pktdma */
+#define CONFIG_KSNAV_PKTDMA_NETCP
 #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE	KS2_NETCP_PDMA_CTRL_BASE
 #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE		KS2_NETCP_PDMA_TX_BASE
 #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM	KS2_NETCP_PDMA_TX_CH_NUM
@@ -134,12 +136,16 @@
 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE
 
 /* Keystone net */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
 #define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
 #define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
 #define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE
 #define CONFIG_KSNET_SERDES_SGMII2_BASE		KS2_SGMII_SERDES2_BASE
 #define CONFIG_KSNET_SERDES_LANES_PER_SGMII	KS2_LANES_PER_SGMII_SERDES
 
+/* SerDes */
+#define CONFIG_TI_KEYSTONE_SERDES
+
 /* AEMIF */
 #define CONFIG_TI_AEMIF
 #define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
@@ -218,6 +224,8 @@
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 
 /* U-Boot general configuration */
 #define CONFIG_SYS_GENERIC_BOARD
@@ -239,30 +247,25 @@
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_EXTRA_ENV_SETTINGS					\
-	"boot=ramfs\0"							\
+	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	"boot=ubi\0"							\
 	"tftp_root=/\0"							\
 	"nfs_root=/export\0"						\
 	"mem_lpae=1\0"							\
 	"mem_reserve=512M\0"						\
 	"addr_fdt=0x87000000\0"						\
 	"addr_kern=0x88000000\0"					\
-	KS2_ADDR_MON							\
 	"addr_uboot=0x87000000\0"					\
 	"addr_fs=0x82000000\0"						\
 	"addr_ubi=0x82000000\0"						\
 	"addr_secdb_key=0xc000000\0"					\
 	"fdt_high=0xffffffff\0"						\
-	KS2_FDT_NAME							\
+	"name_kern=uImage-keystone-evm.bin\0"				\
-	"name_fs=arago-console-image.cpio.gz\0"				\
-	"name_kern=uImage\0"						\
-	KS2_NAME_MON							\
-	NAME_UBOOT							\
-	NAME_UBI							\
 	"run_mon=mon_install ${addr_mon}\0"				\
 	"run_kern=bootm ${addr_kern} - ${addr_fdt}\0"			\
 	"init_net=run args_all args_net\0"				\
 	"init_ubi=run args_all args_ubi; "				\
-		"ubi part ubifs; ubifsmount boot;"			\
+		"ubi part ubifs; ubifsmount ubi:boot;"			\
 		"ubifsload ${addr_secdb_key} securedb.key.bin;\0"       \
 	"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
 	"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0"		\
@@ -276,7 +279,6 @@
 	"burn_uboot_nand=nand erase 0 0x100000; "			\
 		"nand write ${addr_uboot} 0 ${filesize}\0"		\
 	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
-	KS2_ARGS_UBI							\
 	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
 		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
 		"${nfs_options} ip=dhcp\0"				\

include/configs/omap3_igep00x0.h

@@ -29,8 +29,6 @@
 
 #define CONFIG_REVISION_TAG		1
 
-#define CONFIG_SUPPORT_RAW_INITRD
-
 /* define to enable boot progress via leds */
 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
     (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)

include/configs/ti_armv7_common.h

@@ -174,6 +174,7 @@
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
 
 /*
  * Common filesystems support.  When we have removable storage we

include/twl4030.h

@@ -390,6 +390,8 @@
 
 /* Voltage Selection in PM Receiver Module */
 #define TWL4030_PM_RECEIVER_VAUX2_VSEL_18		0x05
+#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28		0x09
+#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18		0x01
 #define TWL4030_PM_RECEIVER_VAUX3_VSEL_28		0x03
 #define TWL4030_PM_RECEIVER_VPLL2_VSEL_18		0x05
 #define TWL4030_PM_RECEIVER_VDAC_VSEL_18		0x03