Add first draft of the MPC8641HPCN doc/README.
Signed-off-by: Jon Loeliger <jdl@jdl.com>
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Haiying Wang
Jon Loeliger
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Freescale MPC8641HPCN board
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===========================
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Created 05/24/2006 Haiying Wang
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-------------------------------
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1. Building U-Boot
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------------------
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The 86xx HPCN code base is known to compile using:
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Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
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$ make MPC8641HPCN_config
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Configuring for MPC8641HPCN board...
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$ make
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2. Switch and Jumper Setting
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----------------------------
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Jumpers:
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J14 Pins 1-2 (near plcc32 socket)
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Switches:
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SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1
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01100 :: CORE = 2.5:1
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10000 :: CORE = 3:1
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11100 :: CORE = 3.5:1
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10100 :: CORE = 4:1
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01110 :: CORE = 4.5:1
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SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz
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001 :: SYSCLK = 40MHz
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SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X
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0100 :: 4X
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0110 :: 6X
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1000 :: 8X
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1010 :: 10X
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1100 :: 12X
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1110 :: 14X
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0000 :: 16X
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SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus
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SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V
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0100000 :: VCORE = 1.11V
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SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
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1 :: VCC_PLAT = 1.0V
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SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root
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SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq
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SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX
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SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash
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0 :: boot from PromJet
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SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower
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halves (virtual banks)
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0 :: normal
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SW5(3) = 0 CFG_FLASHWP = 0 :: not protected
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SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4
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1:1 for PD6
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SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined
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SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined
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SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff
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SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation
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SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ
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SW6(6) = 1 CFG_SERROM_ADDR= 1 ::
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SW6(7) = 1 CFG_MEMDEBUG = 1 ::
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SW6(8) = 1 CFG_DDRDEBUG = 1 ::
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SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
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SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
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SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
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SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
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SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
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SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
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SW8(7) = 1 ACPWR = 1 :: non-battery
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SW8(8) = 0 CFG_IDWP = 0 :: write enable
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3. Flash U-Boot
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---------------
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The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
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It is possible to use either half to boot using u-boot. Switch 5 bit 2
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is used for this purpose.
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0xFF800000 to 0xFFBFFFFF - 4MB
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0xFFC00000 to 0xFFFFFFFF - 4MB
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When this bit is 0, U-Boot is at 0xFFF00000.
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When this bit is 1, U-Boot is at 0xFFB00000.
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Use the above mentioned flash commands to program the other half, and
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use switch 5, bit 2 to alternate between the halves. Note: The booting
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version of U-Boot will always be at 0xFFF00000.
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To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
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tftp 1000000 u-boot.bin
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protect off all
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erase fff00000 ffffffff
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cp.b 1000000 fff00100 80000
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To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
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tftp 1000000 u-boot.bin
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erase ffb00000 ffbfffff
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cp.b 1000000 ffb00100 80000
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4. Memory Map
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-------------
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Memory Range Device Size
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------------ ------ ----
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0x0000_0000 0x7fff_ffff DDR 2G
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0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
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0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
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0xf800_0000 0xf80f_ffff CCSR 1M
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0xf810_0000 0xf81f_ffff PIXIS 1M
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0xf840_0000 0xf840_3fff Stack space 32K
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0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M
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0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M
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0xfe00_0000 0xfeff_ffff Flash(alternate)16M
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0xff00_0000 0xffff_ffff Flash(boot bank)16M
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