mmc: zynq_sdhci: Add support for SD3.0
This patch adds support of SD3.0 for ZynqMP. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu
Michal Simek
parent
b8e25ef16a
commit
d1f4e39d58
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@ -24,6 +24,8 @@ ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),)
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obj-y += $(init-objs)
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endif
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obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
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endif
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@ -0,0 +1,229 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx ZynqMP SoC Tap Delay Programming
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*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#define SD_DLL_CTRL 0xFF180358
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#define SD_ITAP_DLY 0xFF180314
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#define SD_OTAP_DLY 0xFF180318
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#define SD0_DLL_RST_MASK 0x00000004
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#define SD0_DLL_RST 0x00000004
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#define SD1_DLL_RST_MASK 0x00040000
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#define SD1_DLL_RST 0x00040000
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#define SD0_ITAPCHGWIN_MASK 0x00000200
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#define SD0_ITAPCHGWIN 0x00000200
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#define SD1_ITAPCHGWIN_MASK 0x02000000
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#define SD1_ITAPCHGWIN 0x02000000
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#define SD0_ITAPDLYENA_MASK 0x00000100
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#define SD0_ITAPDLYENA 0x00000100
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#define SD1_ITAPDLYENA_MASK 0x01000000
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#define SD1_ITAPDLYENA 0x01000000
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#define SD0_ITAPDLYSEL_MASK 0x000000FF
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#define SD0_ITAPDLYSEL_HSD 0x00000015
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#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003D
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#define SD0_ITAPDLYSEL_MMC_DDR50 0x00000012
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#define SD1_ITAPDLYSEL_MASK 0x00FF0000
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#define SD1_ITAPDLYSEL_HSD 0x00150000
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#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000
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#define SD1_ITAPDLYSEL_MMC_DDR50 0x00120000
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#define SD0_OTAPDLYSEL_MASK 0x0000003F
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#define SD0_OTAPDLYSEL_MMC_HSD 0x00000006
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#define SD0_OTAPDLYSEL_SD_HSD 0x00000005
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#define SD0_OTAPDLYSEL_SDR50 0x00000003
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#define SD0_OTAPDLYSEL_SDR104_B0 0x00000003
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#define SD0_OTAPDLYSEL_SDR104_B2 0x00000002
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#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004
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#define SD0_OTAPDLYSEL_MMC_DDR50 0x00000006
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#define SD1_OTAPDLYSEL_MASK 0x003F0000
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#define SD1_OTAPDLYSEL_MMC_HSD 0x00060000
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#define SD1_OTAPDLYSEL_SD_HSD 0x00050000
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#define SD1_OTAPDLYSEL_SDR50 0x00030000
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#define SD1_OTAPDLYSEL_SDR104_B0 0x00030000
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#define SD1_OTAPDLYSEL_SDR104_B2 0x00020000
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#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000
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#define SD1_OTAPDLYSEL_MMC_DDR50 0x00060000
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#define MMC_BANK2 0x2
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#define MMC_TIMING_UHS_SDR25 1
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#define MMC_TIMING_UHS_SDR50 2
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#define MMC_TIMING_UHS_SDR104 3
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#define MMC_TIMING_UHS_DDR50 4
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#define MMC_TIMING_MMC_HS200 5
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#define MMC_TIMING_SD_HS 6
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#define MMC_TIMING_MMC_DDR52 7
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#define MMC_TIMING_MMC_HS 8
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void zynqmp_dll_reset(u8 deviceid)
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{
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/* Issue DLL Reset */
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
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SD0_DLL_RST);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
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SD1_DLL_RST);
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mdelay(1);
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/* Release DLL Reset */
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
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}
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static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program OTAP */
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if (bank == MMC_BANK2)
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SDR104_B2);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SDR104_B0);
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} else {
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/* Program OTAP */
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if (bank == MMC_BANK2)
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SDR104_B2);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SDR104_B0);
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}
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}
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static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
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SD0_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
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SD0_ITAPDLYENA);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
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SD0_ITAPDLYSEL_HSD);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_MMC_HS)
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_MMC_HSD);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SD_HSD);
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} else {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
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SD1_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
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SD1_ITAPDLYENA);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
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SD1_ITAPDLYSEL_HSD);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_MMC_HS)
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_MMC_HSD);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SD_HSD);
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}
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}
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static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
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SD0_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
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SD0_ITAPDLYENA);
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
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SD0_ITAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
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SD0_ITAPDLYSEL_MMC_DDR50);
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zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_MMC_DDR50);
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} else {
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/* Program ITAP */
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
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SD1_ITAPCHGWIN);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
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SD1_ITAPDLYENA);
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
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SD1_ITAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
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SD1_ITAPDLYSEL_MMC_DDR50);
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zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK, 0x0);
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/* Program OTAP */
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if (timing == MMC_TIMING_UHS_DDR50)
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SD_DDR50);
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else
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_MMC_DDR50);
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}
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}
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static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0) {
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/* Program OTAP */
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zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
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SD0_OTAPDLYSEL_SDR50);
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} else {
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/* Program OTAP */
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zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
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SD1_OTAPDLYSEL_SDR50);
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}
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}
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void arasan_zynqmp_set_tapdelay(u8 deviceid, u8 timing, u8 bank)
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{
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
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SD0_DLL_RST);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
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SD1_DLL_RST);
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switch (timing) {
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case MMC_TIMING_UHS_SDR25:
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arasan_zynqmp_tap_hs(deviceid, timing, bank);
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break;
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case MMC_TIMING_UHS_SDR50:
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arasan_zynqmp_tap_sdr50(deviceid, timing, bank);
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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arasan_zynqmp_tap_sdr104(deviceid, timing, bank);
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break;
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case MMC_TIMING_UHS_DDR50:
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arasan_zynqmp_tap_ddr50(deviceid, timing, bank);
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break;
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}
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if (deviceid == 0)
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zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
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else
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zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
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}
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@ -9,9 +9,11 @@
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include "mmc_private.h"
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <zynqmp_tap_delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -21,15 +23,212 @@ struct arasan_sdhci_plat {
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unsigned int f_max;
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};
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struct arasan_sdhci_priv {
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struct sdhci_host *host;
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u8 deviceid;
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u8 bank;
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u8 no_1p8;
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bool pwrseq;
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};
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#if defined(CONFIG_ARCH_ZYNQMP)
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static const u8 mode2timing[] = {
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[UHS_SDR12] = UHS_SDR12_BUS_SPEED,
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[UHS_SDR25] = UHS_SDR25_BUS_SPEED,
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[UHS_SDR50] = UHS_SDR50_BUS_SPEED,
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[UHS_SDR104] = UHS_SDR104_BUS_SPEED,
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[UHS_DDR50] = UHS_DDR50_BUS_SPEED,
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};
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#define SDHCI_HOST_CTRL2 0x3E
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#define SDHCI_CTRL2_MODE_MASK 0x7
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#define SDHCI_18V_SIGNAL 0x8
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#define SDHCI_CTRL_EXEC_TUNING 0x0040
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#define SDHCI_CTRL_TUNED_CLK 0x80
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#define SDHCI_TUNING_LOOP_COUNT 40
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static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
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{
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u16 clk;
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unsigned long timeout;
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= ~(SDHCI_CLOCK_CARD_EN);
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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/* Issue DLL Reset */
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zynqmp_dll_reset(deviceid);
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/* Wait max 20 ms */
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timeout = 100;
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while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
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& SDHCI_CLOCK_INT_STABLE)) {
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if (timeout == 0) {
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dev_err(mmc_dev(host->mmc),
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": Internal clock never stabilised.\n");
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return;
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}
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timeout--;
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udelay(1000);
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}
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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}
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static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
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{
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struct mmc_cmd cmd;
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struct mmc_data data;
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u32 ctrl;
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struct sdhci_host *host;
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struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
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u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
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u8 deviceid;
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debug("%s\n", __func__);
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host = priv->host;
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deviceid = priv->deviceid;
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ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
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ctrl |= SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
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mdelay(1);
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arasan_zynqmp_dll_reset(host, deviceid);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
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sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
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do {
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cmd.cmdidx = opcode;
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cmd.resp_type = MMC_RSP_R1;
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cmd.cmdarg = 0;
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data.blocksize = 64;
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data.blocks = 1;
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data.flags = MMC_DATA_READ;
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if (tuning_loop_counter-- == 0)
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break;
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if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
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mmc->bus_width == 8)
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data.blocksize = 128;
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sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
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data.blocksize),
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SDHCI_BLOCK_SIZE);
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sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
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sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
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mmc_send_cmd(mmc, &cmd, NULL);
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ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
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if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
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udelay(1);
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} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
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if (tuning_loop_counter < 0) {
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ctrl &= ~SDHCI_CTRL_TUNED_CLK;
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sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
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}
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if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
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printf("%s:Tuning failed\n", __func__);
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return -1;
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}
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udelay(1);
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arasan_zynqmp_dll_reset(host, deviceid);
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/* Enable only interrupts served by the SD controller */
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sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
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SDHCI_INT_ENABLE);
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/* Mask all sdhci interrupt sources */
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sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
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return 0;
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}
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static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
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{
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struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
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struct mmc *mmc = (struct mmc *)host->mmc;
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u8 uhsmode;
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|
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if (!IS_SD(mmc))
|
||||
return;
|
||||
|
||||
uhsmode = mode2timing[mmc->selected_mode];
|
||||
|
||||
if (uhsmode >= UHS_SDR25_BUS_SPEED)
|
||||
arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
|
||||
priv->bank);
|
||||
}
|
||||
|
||||
static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
|
||||
{
|
||||
struct mmc *mmc = (struct mmc *)host->mmc;
|
||||
u32 reg;
|
||||
|
||||
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
|
||||
reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
|
||||
reg |= SDHCI_18V_SIGNAL;
|
||||
sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
|
||||
}
|
||||
|
||||
if (mmc->selected_mode > SD_HS &&
|
||||
mmc->selected_mode <= UHS_DDR50) {
|
||||
reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
|
||||
reg &= ~SDHCI_CTRL2_MODE_MASK;
|
||||
switch (mmc->selected_mode) {
|
||||
case UHS_SDR12:
|
||||
reg |= UHS_SDR12_BUS_SPEED;
|
||||
break;
|
||||
case UHS_SDR25:
|
||||
reg |= UHS_SDR25_BUS_SPEED;
|
||||
break;
|
||||
case UHS_SDR50:
|
||||
reg |= UHS_SDR50_BUS_SPEED;
|
||||
break;
|
||||
case UHS_SDR104:
|
||||
reg |= UHS_SDR104_BUS_SPEED;
|
||||
break;
|
||||
case UHS_DDR50:
|
||||
reg |= UHS_DDR50_BUS_SPEED;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
|
||||
const struct sdhci_ops arasan_ops = {
|
||||
.platform_execute_tuning = &arasan_sdhci_execute_tuning,
|
||||
.set_delay = &arasan_sdhci_set_tapdelay,
|
||||
.set_control_reg = &arasan_sdhci_set_control_reg,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int arasan_sdhci_probe(struct udevice *dev)
|
||||
{
|
||||
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
|
||||
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
||||
struct sdhci_host *host = dev_get_priv(dev);
|
||||
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
|
||||
struct sdhci_host *host;
|
||||
struct clk clk;
|
||||
unsigned long clock;
|
||||
int ret;
|
||||
|
||||
host = priv->host;
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &clk);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to get clock\n");
|
||||
|
|
@ -41,6 +240,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
|
|||
dev_err(dev, "failed to get rate\n");
|
||||
return clock;
|
||||
}
|
||||
|
||||
debug("%s: CLK %ld\n", __func__, clock);
|
||||
|
||||
ret = clk_enable(&clk);
|
||||
|
|
@ -56,6 +256,9 @@ static int arasan_sdhci_probe(struct udevice *dev)
|
|||
host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
|
||||
#endif
|
||||
|
||||
if (priv->no_1p8)
|
||||
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
|
||||
|
||||
host->max_clk = clock;
|
||||
|
||||
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
|
||||
|
|
@ -73,10 +276,28 @@ static int arasan_sdhci_probe(struct udevice *dev)
|
|||
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
|
||||
struct sdhci_host *host = dev_get_priv(dev);
|
||||
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
|
||||
|
||||
host->name = dev->name;
|
||||
host->ioaddr = (void *)devfdt_get_addr(dev);
|
||||
priv->host = calloc(1, sizeof(struct sdhci_host));
|
||||
if (!priv->host)
|
||||
return -1;
|
||||
|
||||
priv->host->name = dev->name;
|
||||
priv->host->ioaddr = (void *)devfdt_get_addr(dev);
|
||||
|
||||
priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
||||
"xlnx,device_id", -1);
|
||||
priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
||||
"xlnx,mio_bank", -1);
|
||||
if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev),
|
||||
"no-1-8-v", NULL))
|
||||
priv->no_1p8 = 1;
|
||||
else
|
||||
priv->no_1p8 = 0;
|
||||
|
||||
#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
|
||||
priv->host->ops = &arasan_ops;
|
||||
#endif
|
||||
|
||||
plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
||||
"max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
|
||||
|
|
@ -104,6 +325,6 @@ U_BOOT_DRIVER(arasan_sdhci_drv) = {
|
|||
.ops = &sdhci_ops,
|
||||
.bind = arasan_sdhci_bind,
|
||||
.probe = arasan_sdhci_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct sdhci_host),
|
||||
.priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
|
||||
.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Xilinx ZynqMP SoC Tap Delay Programming
|
||||
*
|
||||
* Copyright (C) 2018 Xilinx, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ZYNQMP_TAP_DELAY_H__
|
||||
#define __ZYNQMP_TAP_DELAY_H__
|
||||
|
||||
#ifdef CONFIG_ARCH_ZYNQMP
|
||||
void zynqmp_dll_reset(u8 deviceid);
|
||||
void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank);
|
||||
#else
|
||||
inline void zynqmp_dll_reset(u8 deviceid) {}
|
||||
inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue