arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code fine-tunes the behavior of the MMDC controller in order to improve the signal integrity and memory stability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
44189a0328
commit
d339f16911
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@ -13,6 +13,565 @@
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#include <asm/io.h>
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#include <asm/types.h>
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#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
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static int wait_for_bit(void *reg, const uint32_t mask, bool set)
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{
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unsigned int timeout = 1000;
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u32 val;
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while (--timeout) {
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val = readl(reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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udelay(1);
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}
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printf("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
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__func__, reg, mask, set);
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hang(); /* DRAM couldn't be calibrated, game over :-( */
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}
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static void reset_read_data_fifos(void)
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{
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struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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/* Reset data FIFOs twice. */
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setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
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wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
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setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
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wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0);
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}
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static void precharge_all(const bool cs0_enable, const bool cs1_enable)
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{
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struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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/*
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* Issue the Precharge-All command to the DDR device for both
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* chip selects. Note, CON_REQ bit should also remain set. If
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* only using one chip select, then precharge only the desired
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* chip select.
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*/
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if (cs0_enable) { /* CS0 */
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writel(0x04008050, &mmdc0->mdscr);
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wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
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}
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if (cs1_enable) { /* CS1 */
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writel(0x04008058, &mmdc0->mdscr);
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wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
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}
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}
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static void force_delay_measurement(int bus_size)
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{
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struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
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writel(0x800, &mmdc0->mpmur0);
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if (bus_size == 0x2)
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writel(0x800, &mmdc1->mpmur0);
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}
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static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
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{
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u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
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/*
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* DQS gating absolute offset should be modified from reflecting
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* (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
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*/
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val_ctrl = readl(reg_ctrl);
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val_ctrl &= 0xf0000000;
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dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
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dg_dl_abs_offset = dg_tmp_val & 0x7f;
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dg_hc_del = (dg_tmp_val & 0x780) << 1;
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val_ctrl |= dg_dl_abs_offset + dg_hc_del;
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dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
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dg_dl_abs_offset = dg_tmp_val & 0x7f;
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dg_hc_del = (dg_tmp_val & 0x780) << 1;
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val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
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writel(val_ctrl, reg_ctrl);
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}
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int mmdc_do_write_level_calibration(void)
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{
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struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
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u32 esdmisc_val, zq_val;
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u32 errors = 0;
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u32 ldectrl[4];
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u32 ddr_mr1 = 0x4;
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/*
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* Stash old values in case calibration fails,
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* we need to restore them
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*/
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ldectrl[0] = readl(&mmdc0->mpwldectrl0);
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ldectrl[1] = readl(&mmdc0->mpwldectrl1);
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ldectrl[2] = readl(&mmdc1->mpwldectrl0);
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ldectrl[3] = readl(&mmdc1->mpwldectrl1);
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/* disable DDR logic power down timer */
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clrbits_le32(&mmdc0->mdpdc, 0xff00);
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/* disable Adopt power down timer */
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setbits_le32(&mmdc0->mapsr, 0x1);
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debug("Starting write leveling calibration.\n");
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/*
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* 2. disable auto refresh and ZQ calibration
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* before proceeding with Write Leveling calibration
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*/
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esdmisc_val = readl(&mmdc0->mdref);
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writel(0x0000C000, &mmdc0->mdref);
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zq_val = readl(&mmdc0->mpzqhwctrl);
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writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
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/* 3. increase walat and ralat to maximum */
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setbits_le32(&mmdc0->mdmisc,
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(1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
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setbits_le32(&mmdc1->mdmisc,
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(1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
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/*
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* 4 & 5. Configure the external DDR device to enter write-leveling
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* mode through Load Mode Register command.
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* Register setting:
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* Bits[31:16] MR1 value (0x0080 write leveling enable)
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* Bit[9] set WL_EN to enable MMDC DQS output
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* Bits[6:4] set CMD bits for Load Mode Register programming
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* Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
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*/
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writel(0x00808231, &mmdc0->mdscr);
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/* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
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writel(0x00000001, &mmdc0->mpwlgcr);
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/*
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* 7. Upon completion of this process the MMDC de-asserts
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* the MPWLGCR[HW_WL_EN]
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*/
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wait_for_bit(&mmdc0->mpwlgcr, 1 << 0, 0);
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/*
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* 8. check for any errors: check both PHYs for x64 configuration,
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* if x32, check only PHY0
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*/
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if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
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errors |= 1;
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if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
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errors |= 2;
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debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
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/* check to see if cal failed */
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if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
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(readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
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(readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
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(readl(&mmdc1->mpwldectrl1) == 0x001F001F)) {
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debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
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writel(ldectrl[0], &mmdc0->mpwldectrl0);
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writel(ldectrl[1], &mmdc0->mpwldectrl1);
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writel(ldectrl[2], &mmdc1->mpwldectrl0);
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writel(ldectrl[3], &mmdc1->mpwldectrl1);
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errors |= 4;
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}
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/*
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* User should issue MRS command to exit write leveling mode
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* through Load Mode Register command
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* Register setting:
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* Bits[31:16] MR1 value "ddr_mr1" value from initialization
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* Bit[9] clear WL_EN to disable MMDC DQS output
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* Bits[6:4] set CMD bits for Load Mode Register programming
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* Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
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*/
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writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
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/* re-enable auto refresh and zq cal */
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writel(esdmisc_val, &mmdc0->mdref);
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writel(zq_val, &mmdc0->mpzqhwctrl);
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debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
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readl(&mmdc0->mpwldectrl0));
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debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
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readl(&mmdc0->mpwldectrl1));
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debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
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readl(&mmdc1->mpwldectrl0));
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debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
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readl(&mmdc1->mpwldectrl1));
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/* We must force a readback of these values, to get them to stick */
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readl(&mmdc0->mpwldectrl0);
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readl(&mmdc0->mpwldectrl1);
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readl(&mmdc1->mpwldectrl0);
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readl(&mmdc1->mpwldectrl1);
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/* enable DDR logic power down timer: */
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setbits_le32(&mmdc0->mdpdc, 0x00005500);
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/* Enable Adopt power down timer: */
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clrbits_le32(&mmdc0->mapsr, 0x1);
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/* Clear CON_REQ */
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writel(0, &mmdc0->mdscr);
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return errors;
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}
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int mmdc_do_dqs_calibration(void)
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{
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struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
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struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
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struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
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(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
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bool cs0_enable;
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bool cs1_enable;
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bool cs0_enable_initial;
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bool cs1_enable_initial;
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u32 esdmisc_val;
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u32 bus_size;
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u32 temp_ref;
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u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
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u32 errors = 0;
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u32 initdelay = 0x40404040;
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/* check to see which chip selects are enabled */
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cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
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cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
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/* disable DDR logic power down timer: */
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clrbits_le32(&mmdc0->mdpdc, 0xff00);
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/* disable Adopt power down timer: */
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setbits_le32(&mmdc0->mapsr, 0x1);
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/* set DQS pull ups */
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setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
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setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
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setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
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setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
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setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
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setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
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setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
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setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
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/* Save old RALAT and WALAT values */
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esdmisc_val = readl(&mmdc0->mdmisc);
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setbits_le32(&mmdc0->mdmisc,
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(1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
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/* Disable auto refresh before proceeding with calibration */
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temp_ref = readl(&mmdc0->mdref);
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writel(0x0000c000, &mmdc0->mdref);
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/*
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* Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
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* this also sets the CON_REQ bit.
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*/
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if (cs0_enable_initial)
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writel(0x00008020, &mmdc0->mdscr);
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if (cs1_enable_initial)
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writel(0x00008028, &mmdc0->mdscr);
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/* poll to make sure the con_ack bit was asserted */
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wait_for_bit(&mmdc0->mdscr, 1 << 14, 1);
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/*
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* Check MDMISC register CALIB_PER_CS to see which CS calibration
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* is targeted to (under normal cases, it should be cleared
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* as this is the default value, indicating calibration is directed
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* to CS0).
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* Disable the other chip select not being target for calibration
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* to avoid any potential issues. This will get re-enabled at end
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* of calibration.
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*/
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if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
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clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
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else
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clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
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/*
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* Check to see which chip selects are now enabled for
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* the remainder of the calibration.
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*/
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cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
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cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
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/* Check to see what the data bus size is */
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bus_size = (readl(&mmdc0->mdctl) & 0x30000) >> 16;
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debug("Data bus size: %d (%d bits)\n", bus_size, 1 << (bus_size + 4));
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precharge_all(cs0_enable, cs1_enable);
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/* Write the pre-defined value into MPPDCMPR1 */
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writel(pddword, &mmdc0->mppdcmpr1);
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/*
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* Issue a write access to the external DDR device by setting
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* the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
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* this bit until it clears to indicate completion of the write access.
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*/
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setbits_le32(&mmdc0->mpswdar0, 1);
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wait_for_bit(&mmdc0->mpswdar0, 1 << 0, 0);
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/* Set the RD_DL_ABS# bits to their default values
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* (will be calibrated later in the read delay-line calibration).
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* Both PHYs for x64 configuration, if x32, do only PHY0.
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*/
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writel(initdelay, &mmdc0->mprddlctl);
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if (bus_size == 0x2)
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writel(initdelay, &mmdc1->mprddlctl);
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/* Force a measurment, for previous delay setup to take effect. */
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force_delay_measurement(bus_size);
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/*
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* ***************************
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* Read DQS Gating calibration
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* ***************************
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*/
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debug("Starting Read DQS Gating calibration.\n");
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/*
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* Reset the read data FIFOs (two resets); only need to issue reset
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* to PHY0 since in x64 mode, the reset will also go to PHY1.
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*/
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reset_read_data_fifos();
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/*
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* Start the automatic read DQS gating calibration process by
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* asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
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* and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
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* to indicate completion.
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* Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
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* no errors were seen during calibration.
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*/
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/*
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* Set bit 30: chooses option to wait 32 cycles instead of
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* 16 before comparing read data.
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*/
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setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
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/* Set bit 28 to start automatic read DQS gating calibration */
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setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
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/* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
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wait_for_bit(&mmdc0->mpdgctrl0, 1 << 28, 0);
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/*
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* Check to see if any errors were encountered during calibration
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* (check MPDGCTRL0[HW_DG_ERR]).
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* Check both PHYs for x64 configuration, if x32, check only PHY0.
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*/
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if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
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errors |= 1;
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if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
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errors |= 2;
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/*
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* DQS gating absolute offset should be modified from
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* reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
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* reflecting (HW_DG_UPx - 0x80)
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*/
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modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
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&mmdc0->mpdgctrl0);
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modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
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&mmdc0->mpdgctrl1);
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if (bus_size == 0x2) {
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modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
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&mmdc1->mpdgctrl0);
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modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
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&mmdc1->mpdgctrl1);
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}
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debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
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/*
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* **********************
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* Read Delay calibration
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* **********************
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*/
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debug("Starting Read Delay calibration.\n");
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reset_read_data_fifos();
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/*
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* 4. Issue the Precharge-All command to the DDR device for both
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* chip selects. If only using one chip select, then precharge
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* only the desired chip select.
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*/
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precharge_all(cs0_enable, cs1_enable);
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/*
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||||
* 9. Read delay-line calibration
|
||||
* Start the automatic read calibration process by asserting
|
||||
* MPRDDLHWCTL[HW_RD_DL_EN].
|
||||
*/
|
||||
writel(0x00000030, &mmdc0->mprddlhwctl);
|
||||
|
||||
/*
|
||||
* 10. poll for completion
|
||||
* MMDC indicates that the write data calibration had finished by
|
||||
* setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
|
||||
* no error bits were set.
|
||||
*/
|
||||
wait_for_bit(&mmdc0->mprddlhwctl, 1 << 4, 0);
|
||||
|
||||
/* check both PHYs for x64 configuration, if x32, check only PHY0 */
|
||||
if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
|
||||
errors |= 4;
|
||||
|
||||
if ((bus_size == 0x2) && (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
|
||||
errors |= 8;
|
||||
|
||||
debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
|
||||
|
||||
/*
|
||||
* ***********************
|
||||
* Write Delay Calibration
|
||||
* ***********************
|
||||
*/
|
||||
debug("Starting Write Delay calibration.\n");
|
||||
|
||||
reset_read_data_fifos();
|
||||
|
||||
/*
|
||||
* 4. Issue the Precharge-All command to the DDR device for both
|
||||
* chip selects. If only using one chip select, then precharge
|
||||
* only the desired chip select.
|
||||
*/
|
||||
precharge_all(cs0_enable, cs1_enable);
|
||||
|
||||
/*
|
||||
* 8. Set the WR_DL_ABS# bits to their default values.
|
||||
* Both PHYs for x64 configuration, if x32, do only PHY0.
|
||||
*/
|
||||
writel(initdelay, &mmdc0->mpwrdlctl);
|
||||
if (bus_size == 0x2)
|
||||
writel(initdelay, &mmdc1->mpwrdlctl);
|
||||
|
||||
/*
|
||||
* XXX This isn't in the manual. Force a measurement,
|
||||
* for previous delay setup to effect.
|
||||
*/
|
||||
force_delay_measurement(bus_size);
|
||||
|
||||
/*
|
||||
* 9. 10. Start the automatic write calibration process
|
||||
* by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
|
||||
*/
|
||||
writel(0x00000030, &mmdc0->mpwrdlhwctl);
|
||||
|
||||
/*
|
||||
* Poll for completion.
|
||||
* MMDC indicates that the write data calibration had finished
|
||||
* by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
|
||||
* Also, ensure that no error bits were set.
|
||||
*/
|
||||
wait_for_bit(&mmdc0->mpwrdlhwctl, 1 << 4, 0);
|
||||
|
||||
/* Check both PHYs for x64 configuration, if x32, check only PHY0 */
|
||||
if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
|
||||
errors |= 16;
|
||||
|
||||
if ((bus_size == 0x2) && (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
|
||||
errors |= 32;
|
||||
|
||||
debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
|
||||
|
||||
reset_read_data_fifos();
|
||||
|
||||
/* Enable DDR logic power down timer */
|
||||
setbits_le32(&mmdc0->mdpdc, 0x00005500);
|
||||
|
||||
/* Enable Adopt power down timer */
|
||||
clrbits_le32(&mmdc0->mapsr, 0x1);
|
||||
|
||||
/* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
|
||||
writel(esdmisc_val, &mmdc0->mdmisc);
|
||||
|
||||
/* Clear DQS pull ups */
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000);
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000);
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000);
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000);
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000);
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000);
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000);
|
||||
clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000);
|
||||
|
||||
/* Re-enable SDE (chip selects) if they were set initially */
|
||||
if (cs1_enable_initial)
|
||||
/* Set SDE_1 */
|
||||
setbits_le32(&mmdc0->mdctl, 1 << 30);
|
||||
|
||||
if (cs0_enable_initial)
|
||||
/* Set SDE_0 */
|
||||
setbits_le32(&mmdc0->mdctl, 1 << 31);
|
||||
|
||||
/* Re-enable to auto refresh */
|
||||
writel(temp_ref, &mmdc0->mdref);
|
||||
|
||||
/* Clear the MDSCR (including the con_req bit) */
|
||||
writel(0x0, &mmdc0->mdscr); /* CS0 */
|
||||
|
||||
/* Poll to make sure the con_ack bit is clear */
|
||||
wait_for_bit(&mmdc0->mdscr, 1 << 14, 0);
|
||||
|
||||
/*
|
||||
* Print out the registers that were updated as a result
|
||||
* of the calibration process.
|
||||
*/
|
||||
debug("MMDC registers updated from calibration\n");
|
||||
debug("Read DQS gating calibration:\n");
|
||||
debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
|
||||
debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
|
||||
debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
|
||||
debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
|
||||
debug("Read calibration:\n");
|
||||
debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
|
||||
debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
|
||||
debug("Write calibration:\n");
|
||||
debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
|
||||
debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
|
||||
|
||||
/*
|
||||
* Registers below are for debugging purposes. These print out
|
||||
* the upper and lower boundaries captured during
|
||||
* read DQS gating calibration.
|
||||
*/
|
||||
debug("Status registers bounds for read DQS gating:\n");
|
||||
debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
|
||||
debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
|
||||
debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
|
||||
debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
|
||||
debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
|
||||
debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
|
||||
debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
|
||||
debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
|
||||
|
||||
debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
|
||||
|
||||
return errors;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX6SX)
|
||||
/* Configure MX6SX mmdc iomux */
|
||||
void mx6sx_dram_iocfg(unsigned width,
|
||||
|
|
|
|||
|
|
@ -456,6 +456,11 @@ void mx6sl_dram_iocfg(unsigned width,
|
|||
const struct mx6sl_iomux_ddr_regs *,
|
||||
const struct mx6sl_iomux_grp_regs *);
|
||||
|
||||
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
|
||||
int mmdc_do_write_level_calibration(void);
|
||||
int mmdc_do_dqs_calibration(void);
|
||||
#endif
|
||||
|
||||
/* configure mx6 mmdc registers */
|
||||
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
|
||||
const struct mx6_mmdc_calibration *,
|
||||
|
|
|
|||
Loading…
Reference in New Issue