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NAND: davinci: Fix warnings when 4-bit ECC not used 

I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2009-09-28 16:33:18 -05:00
parent ca6189db48
commit d44e9c1736
1 changed files with 1 additions and 2 deletions
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3
drivers/mtd/nand/davinci_nand.c
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@ -202,7 +202,6 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
}, },
#endif #endif
}; };
#endif
static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{ {
@ -289,7 +288,6 @@ static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc, uint8_t *calc_ecc) uint8_t *read_ecc, uint8_t *calc_ecc)
{ {
struct nand_chip *this = mtd->priv;
unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
int i; int i;
unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0; unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
@ -441,6 +439,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
return numerrors; return numerrors;
} }
#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
static int nand_davinci_dev_ready(struct mtd_info *mtd) static int nand_davinci_dev_ready(struct mtd_info *mtd)
{ {