ram: stm32mp1: compute DDR size from DDRCTL registers
Compute the DDR size from DDR controller register (mstr and addrmap) in U-Boot proper as the DDR information are useful only for SPL but not for U-Boot proper, for example with TFABOOT. This patch simplify U-Boot DT when several DDR size are supported and support of next SOC in STM32MP family. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Patrick Delaunay
Patrice Chotard
parent
e84ee40b0b
commit
d72e7bbe7c
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@ -239,6 +239,7 @@ struct stm32mp1_ddrphy {
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#define DDRCTRL_MSTR_LPDDR2 BIT(2)
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#define DDRCTRL_MSTR_LPDDR3 BIT(3)
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#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
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#define DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT 12
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#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL (0 << 12)
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#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF (1 << 12)
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#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER (2 << 12)
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@ -16,6 +16,12 @@
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include "stm32mp1_ddr.h"
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#include "stm32mp1_ddr_regs.h"
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/* DDR subsystem configuration */
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struct stm32mp1_ddr_cfg {
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u8 nb_bytes; /* MEMC_DRAM_DATA_WIDTH */
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};
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static const char *const clkname[] = {
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"ddrc1",
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@ -165,6 +171,183 @@ static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
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return 0;
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}
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static u8 get_data_bus_width(struct stm32mp1_ddrctl *ctl)
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{
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u32 reg = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
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u8 data_bus_width = reg >> DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT;
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return data_bus_width;
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}
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static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
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{
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/* Count bank address bits */
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u8 bits = 0;
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u32 reg, val;
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reg = readl(&ctl->addrmap1);
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/* addrmap1.addrmap_bank_b1 */
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val = (reg & GENMASK(5, 0)) >> 0;
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if (val <= 31)
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bits++;
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/* addrmap1.addrmap_bank_b2 */
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val = (reg & GENMASK(13, 8)) >> 8;
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if (val <= 31)
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bits++;
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/* addrmap1.addrmap_bank_b3 */
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val = (reg & GENMASK(21, 16)) >> 16;
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if (val <= 31)
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bits++;
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return bits;
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}
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static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width)
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{
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u8 bits;
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u32 reg, val;
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/* Count column address bits, start at 2 for b0 and b1 (fixed) */
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bits = 2;
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reg = readl(&ctl->addrmap2);
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/* addrmap2.addrmap_col_b2 */
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val = (reg & GENMASK(3, 0)) >> 0;
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if (val <= 7)
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bits++;
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/* addrmap2.addrmap_col_b3 */
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val = (reg & GENMASK(11, 8)) >> 8;
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if (val <= 7)
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bits++;
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/* addrmap2.addrmap_col_b4 */
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val = (reg & GENMASK(19, 16)) >> 16;
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if (val <= 7)
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bits++;
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/* addrmap2.addrmap_col_b5 */
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val = (reg & GENMASK(27, 24)) >> 24;
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if (val <= 7)
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bits++;
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reg = readl(&ctl->addrmap3);
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/* addrmap3.addrmap_col_b6 */
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val = (reg & GENMASK(3, 0)) >> 0;
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if (val <= 7)
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bits++;
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/* addrmap3.addrmap_col_b7 */
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val = (reg & GENMASK(11, 8)) >> 8;
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if (val <= 7)
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bits++;
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/* addrmap3.addrmap_col_b8 */
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val = (reg & GENMASK(19, 16)) >> 16;
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if (val <= 7)
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bits++;
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/* addrmap3.addrmap_col_b9 */
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val = (reg & GENMASK(27, 24)) >> 24;
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if (val <= 7)
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bits++;
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reg = readl(&ctl->addrmap4);
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/* addrmap4.addrmap_col_b10 */
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val = (reg & GENMASK(3, 0)) >> 0;
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if (val <= 7)
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bits++;
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/* addrmap4.addrmap_col_b11 */
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val = (reg & GENMASK(11, 8)) >> 8;
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if (val <= 7)
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bits++;
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/*
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* column bits shift up:
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* 1 when half the data bus is used (data_bus_width = 1)
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* 2 when a quarter the data bus is used (data_bus_width = 2)
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* nothing to do for full data bus (data_bus_width = 0)
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*/
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bits += data_bus_width;
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return bits;
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}
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static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
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{
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/* Count row address bits */
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u8 bits = 0;
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u32 reg, val;
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reg = readl(&ctl->addrmap5);
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/* addrmap5.addrmap_row_b0 */
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val = (reg & GENMASK(3, 0)) >> 0;
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if (val <= 11)
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bits++;
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/* addrmap5.addrmap_row_b1 */
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val = (reg & GENMASK(11, 8)) >> 8;
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if (val <= 11)
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bits++;
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/* addrmap5.addrmap_row_b2_10 */
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val = (reg & GENMASK(19, 16)) >> 16;
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if (val <= 11)
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bits += 9;
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else
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printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
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/* addrmap5.addrmap_row_b11 */
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val = (reg & GENMASK(27, 24)) >> 24;
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if (val <= 11)
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bits++;
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reg = readl(&ctl->addrmap6);
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/* addrmap6.addrmap_row_b12 */
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val = (reg & GENMASK(3, 0)) >> 0;
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if (val <= 7)
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bits++;
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/* addrmap6.addrmap_row_b13 */
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val = (reg & GENMASK(11, 8)) >> 8;
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if (val <= 7)
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bits++;
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/* addrmap6.addrmap_row_b14 */
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val = (reg & GENMASK(19, 16)) >> 16;
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if (val <= 7)
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bits++;
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/* addrmap6.addrmap_row_b15 */
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val = (reg & GENMASK(27, 24)) >> 24;
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if (val <= 7)
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bits++;
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return bits;
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}
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/*
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* stm32mp1_ddr_size
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*
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* Get the current DRAM size from the DDR CTL registers
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*
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* @return: DRAM size
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*/
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u32 stm32mp1_ddr_size(struct udevice *dev)
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{
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u8 nb_bit;
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u32 ddr_size;
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u8 data_bus_width;
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struct ddr_info *priv = dev_get_priv(dev);
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struct stm32mp1_ddrctl *ctl = priv->ctl;
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struct stm32mp1_ddr_cfg *cfg = (struct stm32mp1_ddr_cfg *)dev_get_driver_data(dev);
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const u8 nb_bytes = cfg->nb_bytes;
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data_bus_width = get_data_bus_width(ctl);
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nb_bit = get_nb_bank(ctl) + get_nb_col(ctl, data_bus_width) +
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get_nb_row(ctl);
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if (nb_bit > 32) {
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nb_bit = 32;
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debug("invalid DDR configuration: %d bits\n", nb_bit);
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}
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ddr_size = (nb_bytes >> data_bus_width) << nb_bit;
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if (ddr_size > STM32_DDR_SIZE) {
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ddr_size = STM32_DDR_SIZE;
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debug("invalid DDR configuration: size = %x\n", ddr_size);
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}
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return ddr_size;
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}
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static int stm32mp1_ddr_probe(struct udevice *dev)
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{
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struct ddr_info *priv = dev_get_priv(dev);
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@ -191,8 +374,8 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
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return log_ret(ret);
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}
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ofnode node = stm32mp1_ddr_get_ofnode(dev);
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priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
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priv->info.size = stm32mp1_ddr_size(dev);
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return 0;
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}
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@ -209,8 +392,12 @@ static struct ram_ops stm32mp1_ddr_ops = {
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.get_info = stm32mp1_ddr_get_info,
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};
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static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = {
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.nb_bytes = 4,
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};
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static const struct udevice_id stm32mp1_ddr_ids[] = {
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{ .compatible = "st,stm32mp1-ddr" },
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{ .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},
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{ }
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};
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