mmc: s3c: Add SD driver
Implement SD driver for the S3C24xx family. This implementation is currently only capable of using the PIO transfers, DMA is not supported. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
This commit is contained in:
Marek Vasut
Pantelis Antoniou
parent
7eca6b6327
commit
dae0f5c644
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@ -700,4 +700,10 @@ struct s3c24x0_sdi {
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#endif
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#endif
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};
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};
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#ifdef CONFIG_CMD_MMC
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#include <mmc.h>
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int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
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int (*getwp)(struct mmc *));
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#endif
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#endif /*__S3C24X0_H__*/
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#endif /*__S3C24X0_H__*/
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@ -22,6 +22,7 @@ obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
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obj-$(CONFIG_SDHCI) += sdhci.o
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obj-$(CONFIG_SDHCI) += sdhci.o
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obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
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obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
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obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
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obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
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obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
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obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
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obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
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obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
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obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
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@ -0,0 +1,321 @@
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/*
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* S3C24xx SD/MMC driver
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*
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* Based on OpenMoko S3C24xx driver by Harald Welte <laforge@openmoko.org>
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*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <errno.h>
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#include <asm/arch/s3c24x0_cpu.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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#define S3C2440_SDICON_SDRESET (1 << 8)
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#define S3C2410_SDICON_FIFORESET (1 << 1)
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#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
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#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
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#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
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#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
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#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
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#define S3C2410_SDICMDCON_INDEX 0x3f
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#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
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#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
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#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
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#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
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#define S3C2440_SDIDCON_DS_WORD (2 << 22)
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#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
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#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
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#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
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#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
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#define S3C2440_SDIDCON_DATSTART (1 << 14)
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#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
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#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
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#define S3C2410_SDIDCON_BLKNUM 0x7ff
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#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
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#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
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#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
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#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
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#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
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#define S3C2410_SDIFSTA_TFHALF (1 << 11)
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#define S3C2410_SDIFSTA_COUNTMASK 0x7f
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/*
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* WARNING: We only support one SD IP block.
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* NOTE: It's not likely there will ever exist an S3C24xx with two,
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* at least not in this universe all right.
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*/
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static int wide_bus;
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static int
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s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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{
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struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
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uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta;
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uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT;
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unsigned int timeout = 100000;
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int ret = 0, xfer_len, data_offset = 0;
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const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL |
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S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL |
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S3C2410_SDIDSTA_DATATIMEOUT;
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writel(0xffffffff, &sdi_regs->sdicsta);
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writel(0xffffffff, &sdi_regs->sdidsta);
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writel(0xffffffff, &sdi_regs->sdifsta);
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/* Set up data transfer (if applicable). */
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if (data) {
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writel(data->blocksize, &sdi_regs->sdibsize);
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sdidcon = data->blocks & S3C2410_SDIDCON_BLKNUM;
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sdidcon |= S3C2410_SDIDCON_BLOCKMODE;
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#if defined(CONFIG_S3C2440)
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sdidcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
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#endif
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if (wide_bus)
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sdidcon |= S3C2410_SDIDCON_WIDEBUS;
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if (data->flags & MMC_DATA_READ) {
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sdidcon |= S3C2410_SDIDCON_RXAFTERCMD;
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sdidcon |= S3C2410_SDIDCON_XFER_RXSTART;
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} else {
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sdidcon |= S3C2410_SDIDCON_TXAFTERRESP;
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sdidcon |= S3C2410_SDIDCON_XFER_TXSTART;
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}
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writel(sdidcon, &sdi_regs->sdidcon);
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}
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/* Write CMD arg. */
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writel(cmd->cmdarg, &sdi_regs->sdicarg);
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/* Write CMD index. */
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sdiccon = cmd->cmdidx & S3C2410_SDICMDCON_INDEX;
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sdiccon |= S3C2410_SDICMDCON_SENDERHOST;
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sdiccon |= S3C2410_SDICMDCON_CMDSTART;
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/* Command with short response. */
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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sdiccon |= S3C2410_SDICMDCON_WAITRSP;
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sdicsta_wait_bit = S3C2410_SDICMDSTAT_RSPFIN;
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}
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/* Command with long response. */
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if (cmd->resp_type & MMC_RSP_136)
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sdiccon |= S3C2410_SDICMDCON_LONGRSP;
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/* Start the command. */
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writel(sdiccon, &sdi_regs->sdiccon);
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/* Wait for the command to complete or for response. */
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for (timeout = 100000; timeout; timeout--) {
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sdicsta = readl(&sdi_regs->sdicsta);
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if (sdicsta & sdicsta_wait_bit)
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break;
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if (sdicsta & S3C2410_SDICMDSTAT_CMDTIMEOUT)
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timeout = 1;
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}
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/* Clean the status bits. */
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setbits_le32(&sdi_regs->sdicsta, 0xf << 9);
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if (!timeout) {
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puts("S3C SDI: Command timed out!\n");
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ret = TIMEOUT;
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goto error;
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}
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/* Read out the response. */
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[0] = readl(&sdi_regs->sdirsp0);
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cmd->response[1] = readl(&sdi_regs->sdirsp1);
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cmd->response[2] = readl(&sdi_regs->sdirsp2);
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cmd->response[3] = readl(&sdi_regs->sdirsp3);
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} else {
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cmd->response[0] = readl(&sdi_regs->sdirsp0);
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}
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/* If there are no data, we're done. */
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if (!data)
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return 0;
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xfer_len = data->blocksize * data->blocks;
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while (xfer_len > 0) {
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sdidsta = readl(&sdi_regs->sdidsta);
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sdifsta = readl(&sdi_regs->sdifsta);
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if (sdidsta & sdidsta_err_mask) {
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printf("S3C SDI: Data error (sdta=0x%08x)\n", sdidsta);
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ret = -EIO;
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goto error;
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}
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if (data->flags & MMC_DATA_READ) {
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if ((sdifsta & S3C2410_SDIFSTA_COUNTMASK) < 4)
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continue;
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sdidat = readl(&sdi_regs->sdidat);
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put_unaligned_le32(sdidat, data->dest + data_offset);
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} else { /* Write */
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/* TX FIFO half full. */
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if (!(sdifsta & S3C2410_SDIFSTA_TFHALF))
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continue;
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/* TX FIFO is below 32b full, write. */
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sdidat = get_unaligned_le32(data->src + data_offset);
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writel(sdidat, &sdi_regs->sdidat);
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}
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data_offset += 4;
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xfer_len -= 4;
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}
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/* Wait for the command to complete or for response. */
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for (timeout = 100000; timeout; timeout--) {
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sdidsta = readl(&sdi_regs->sdidsta);
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if (sdidsta & S3C2410_SDIDSTA_XFERFINISH)
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break;
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if (sdidsta & S3C2410_SDIDSTA_DATATIMEOUT)
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timeout = 1;
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}
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/* Clear status bits. */
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writel(0x6f8, &sdi_regs->sdidsta);
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if (!timeout) {
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puts("S3C SDI: Command timed out!\n");
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ret = TIMEOUT;
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goto error;
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}
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writel(0, &sdi_regs->sdidcon);
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return 0;
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error:
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return ret;
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}
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static void s3cmmc_set_ios(struct mmc *mmc)
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{
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struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
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uint32_t divider = 0;
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wide_bus = (mmc->bus_width == 4);
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if (!mmc->clock)
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return;
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divider = DIV_ROUND_UP(get_PCLK(), mmc->clock);
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if (divider)
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divider--;
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writel(divider, &sdi_regs->sdipre);
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mdelay(125);
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}
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static int s3cmmc_init(struct mmc *mmc)
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{
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
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/* Start the clock. */
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setbits_le32(&clk_power->clkcon, 1 << 9);
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#if defined(CONFIG_S3C2440)
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writel(S3C2440_SDICON_SDRESET, &sdi_regs->sdicon);
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mdelay(10);
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writel(0x7fffff, &sdi_regs->sdidtimer);
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#else
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writel(0xffff, &sdi_regs->sdidtimer);
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#endif
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writel(MMC_MAX_BLOCK_LEN, &sdi_regs->sdibsize);
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writel(0x0, &sdi_regs->sdiimsk);
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writel(S3C2410_SDICON_FIFORESET | S3C2410_SDICON_CLOCKTYPE,
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&sdi_regs->sdicon);
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mdelay(125);
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return 0;
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}
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struct s3cmmc_priv {
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struct mmc_config cfg;
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int (*getcd)(struct mmc *);
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int (*getwp)(struct mmc *);
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};
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static int s3cmmc_getcd(struct mmc *mmc)
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{
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struct s3cmmc_priv *priv = mmc->priv;
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if (priv->getcd)
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return priv->getcd(mmc);
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else
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return 0;
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}
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static int s3cmmc_getwp(struct mmc *mmc)
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{
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struct s3cmmc_priv *priv = mmc->priv;
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if (priv->getwp)
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return priv->getwp(mmc);
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else
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return 0;
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}
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static const struct mmc_ops s3cmmc_ops = {
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.send_cmd = s3cmmc_send_cmd,
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.set_ios = s3cmmc_set_ios,
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.init = s3cmmc_init,
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.getcd = s3cmmc_getcd,
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.getwp = s3cmmc_getwp,
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};
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int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
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int (*getwp)(struct mmc *))
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{
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struct s3cmmc_priv *priv;
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struct mmc *mmc;
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struct mmc_config *cfg;
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priv = calloc(1, sizeof(*priv));
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if (!priv)
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return -ENOMEM;
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cfg = &priv->cfg;
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cfg->name = "S3C MMC";
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cfg->ops = &s3cmmc_ops;
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cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS;
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cfg->f_min = 400000;
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cfg->f_max = get_PCLK() / 2;
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cfg->b_max = 0x80;
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#if defined(CONFIG_S3C2410)
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/*
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* S3C2410 has some bug that prevents reliable
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* operation at higher speed
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*/
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cfg->f_max /= 2;
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#endif
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mmc = mmc_create(cfg, priv);
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if (!mmc) {
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free(priv);
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return -ENOMEM;
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}
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return 0;
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}
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