From dc375987b073028fa3b4148aaccca29e90bce063 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Tue, 7 Feb 2023 09:20:15 +0100 Subject: [PATCH] ram: k3-ddrss: Fix a ddr4 controller stall The DDR4 controller might stall indefinitely if we access the same register twice withing a short time interval. This commit makes sure we reuse the previously read value so that we don't have to access twice. See this article for more information: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057242/am6442-access-to-ddr4-controller-register-stalls-indefinitely-while-in-lpddr4-frequency-update --- drivers/ram/k3-ddrss/k3-ddrss.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 7e445d2b73..ed846b656c 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -241,15 +241,13 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) } } +static u32 dram_class = DENALI_CTL_0_DRAM_CLASS_LPDDR4; static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) { - u32 dram_class; struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); - dram_class = k3_lpddr4_read_ddr_type(pd); - switch (dram_class) { case DENALI_CTL_0_DRAM_CLASS_DDR4: break; @@ -263,7 +261,6 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) { - u32 dram_class; int ret; lpddr4_privatedata *pd = &ddrss->pd;