arm: dts: ti: k3-am654-base-board: add ICSSG2 Ethernet support
Add ICSSG2 EMAC support. DT nodes are fetch from kernel 5.10 Add U-Boot specific properties are kept under k3-am654-base-board-u-boot.dtsi Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
Praneeth Bajjuri
parent
80a20d40ec
commit
dc986a309a
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@ -76,3 +76,37 @@
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&tx_pru2_1 {
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&tx_pru2_1 {
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remoteproc-name = "tx_pru2_1";
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remoteproc-name = "tx_pru2_1";
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};
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};
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&oc_sram {
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icssg0_sram: icssg0-sram@40000 {
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reg = <0x40000 0x10000>;
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};
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icssg1_sram: icssg1-sram@50000 {
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reg = <0x50000 0x10000>;
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};
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icssg2_sram: icssg2-sram@60000 {
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reg = <0x60000 0x10000>;
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};
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};
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&icssg2_eth {
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sram = <&icssg2_sram>;
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pinctrl-0 = <&icssg2_rgmii_pins_default &icssg2_mdio_pins_default>;
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/* Use MCU DMA channels */
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dmas = <&mcu_udmap 0xc300>, /* egress slice 0 */
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<&mcu_udmap 0xc301>, /* egress slice 0 */
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<&mcu_udmap 0xc302>, /* egress slice 0 */
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<&mcu_udmap 0xc303>, /* egress slice 0 */
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<&mcu_udmap 0xc304>, /* egress slice 1 */
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<&mcu_udmap 0xc305>, /* egress slice 1 */
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<&mcu_udmap 0xc306>, /* egress slice 1 */
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<&mcu_udmap 0xc307>, /* egress slice 1 */
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<&mcu_udmap 0x4300>, /* ingress slice 0 */
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<&mcu_udmap 0x4301>, /* ingress slice 1 */
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<&mcu_udmap 0x4302>, /* mgmnt rsp slice 0 */
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<&mcu_udmap 0x4303>; /* mgmnt rsp slice 1 */
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};
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/* Disable ICSSG2 EMAC1 */
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/delete-node/ &icssg2_emac1;
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@ -7,6 +7,7 @@
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#include "k3-am654.dtsi"
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#include "k3-am654.dtsi"
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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/ {
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compatible = "ti,am654-evm", "ti,am654";
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compatible = "ti,am654-evm", "ti,am654";
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@ -39,6 +40,71 @@
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no-map;
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no-map;
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};
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};
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};
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};
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/* Dual Ethernet application node on PRU-ICSSG2 */
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icssg2_eth: icssg2-eth {
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compatible = "ti,am654-icssg-prueth";
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pinctrl-names = "default";
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pinctrl-0 = <&icssg2_rgmii_pins_default>;
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sram = <&msmc_ram>;
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ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
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<&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
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firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
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ti,pruss-gp-mux-sel = <2>, /* MII mode */
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<2>,
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<2>,
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<2>, /* MII mode */
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<2>,
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<2>;
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mii-g-rt = <&icssg2_mii_g_rt>;
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mii-rt = <&icssg2_mii_rt>;
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iep = <&icssg2_iep0>, <&icssg2_iep1>;
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interrupt-parent = <&icssg2_intc>;
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interrupts = <24 0 2>, <25 1 3>;
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interrupt-names = "tx_ts0", "tx_ts1";
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dmas = <&main_udmap 0xc300>, /* egress slice 0 */
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<&main_udmap 0xc301>, /* egress slice 0 */
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<&main_udmap 0xc302>, /* egress slice 0 */
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<&main_udmap 0xc303>, /* egress slice 0 */
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<&main_udmap 0xc304>, /* egress slice 1 */
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<&main_udmap 0xc305>, /* egress slice 1 */
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<&main_udmap 0xc306>, /* egress slice 1 */
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<&main_udmap 0xc307>, /* egress slice 1 */
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<&main_udmap 0x4300>, /* ingress slice 0 */
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<&main_udmap 0x4301>, /* ingress slice 1 */
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<&main_udmap 0x4302>, /* mgmnt rsp slice 0 */
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<&main_udmap 0x4303>; /* mgmnt rsp slice 1 */
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dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
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"tx1-0", "tx1-1", "tx1-2", "tx1-3",
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"rx0", "rx1",
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"rxmgm0", "rxmgm1";
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icssg2_emac0: ethernet-mii0 {
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phy-handle = <&icssg2_phy0>;
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phy-mode = "rgmii-rxid";
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syscon-rgmii-delay = <&scm_conf 0x4120>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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icssg2_emac1: ethernet-mii1 {
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phy-handle = <&icssg2_phy1>;
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phy-mode = "rgmii-rxid";
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syscon-rgmii-delay = <&scm_conf 0x4124>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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};
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};
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};
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&main_pmx0 {
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&main_pmx0 {
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@ -84,6 +150,43 @@
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AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
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AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
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>;
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>;
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};
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};
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icssg2_mdio_pins_default: icssg2-mdio-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
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AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
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>;
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};
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icssg2_rgmii_pins_default: icssg2-rgmii-pins-default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
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AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
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AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
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AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
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AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
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AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
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AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
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AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
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AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
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AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
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AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
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AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
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AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
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AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
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AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
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AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
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AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
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AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
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AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
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AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
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AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
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AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
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AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
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AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
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>;
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};
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};
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};
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&main_pmx1 {
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&main_pmx1 {
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@ -228,3 +331,21 @@
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#size-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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};
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&icssg2_mdio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&icssg2_mdio_pins_default>;
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icssg2_phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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icssg2_phy1: ethernet-phy@3 {
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reg = <3>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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