ARM: dts: imx: Adjust ECSPI1 pinmux on i.MX8M Plus DHCOM
The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com>
This commit is contained in:
		
							parent
							
								
									866a33e478
								
							
						
					
					
						commit
						dd5ca87464
					
				| 
						 | 
					@ -70,7 +70,7 @@
 | 
				
			||||||
&ecspi1 {
 | 
					&ecspi1 {
 | 
				
			||||||
	pinctrl-names = "default";
 | 
						pinctrl-names = "default";
 | 
				
			||||||
	pinctrl-0 = <&pinctrl_ecspi1>;
 | 
						pinctrl-0 = <&pinctrl_ecspi1>;
 | 
				
			||||||
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 | 
						cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
 | 
				
			||||||
	status = "disabled";
 | 
						status = "disabled";
 | 
				
			||||||
};
 | 
					};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
| 
						 | 
					@ -660,10 +660,10 @@
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	pinctrl_ecspi1: dhcom-ecspi1-grp {
 | 
						pinctrl_ecspi1: dhcom-ecspi1-grp {
 | 
				
			||||||
		fsl,pins = <
 | 
							fsl,pins = <
 | 
				
			||||||
			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x44
 | 
								MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44
 | 
				
			||||||
			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x44
 | 
								MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44
 | 
				
			||||||
			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x44
 | 
								MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44
 | 
				
			||||||
			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40
 | 
								MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40
 | 
				
			||||||
		>;
 | 
							>;
 | 
				
			||||||
	};
 | 
						};
 | 
				
			||||||
 | 
					
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
		Loading…
	
		Reference in New Issue