Merge branch 'master' of git://git.denx.de/u-boot-sunxi
This commit is contained in:
		
						commit
						dd758c6720
					
				|  | @ -476,6 +476,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \ | ||||||
| 	sun50i-a64-amarula-relic.dtb \
 | 	sun50i-a64-amarula-relic.dtb \
 | ||||||
| 	sun50i-a64-bananapi-m64.dtb \
 | 	sun50i-a64-bananapi-m64.dtb \
 | ||||||
| 	sun50i-a64-nanopi-a64.dtb \
 | 	sun50i-a64-nanopi-a64.dtb \
 | ||||||
|  | 	sun50i-a64-oceanic-5205-5inmfd.dtb \
 | ||||||
| 	sun50i-a64-olinuxino.dtb \
 | 	sun50i-a64-olinuxino.dtb \
 | ||||||
| 	sun50i-a64-orangepi-win.dtb \
 | 	sun50i-a64-orangepi-win.dtb \
 | ||||||
| 	sun50i-a64-pine64-lts.dtb \
 | 	sun50i-a64-pine64-lts.dtb \
 | ||||||
|  |  | ||||||
|  | @ -0,0 +1,68 @@ | ||||||
|  | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) | ||||||
|  | /* | ||||||
|  |  * Copyright (C) 2019 Oceanic Systems (UK) Ltd. | ||||||
|  |  * Copyright (C) 2019 Amarula Solutions B.V. | ||||||
|  |  * Author: Jagan Teki <jagan@amarulasolutions.com> | ||||||
|  |  */ | ||||||
|  | 
 | ||||||
|  | /dts-v1/; | ||||||
|  | 
 | ||||||
|  | #include "sun50i-a64-sopine.dtsi" | ||||||
|  | 
 | ||||||
|  | / { | ||||||
|  | 	model = "Oceanic 5205 5inMFD"; | ||||||
|  | 	compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64"; | ||||||
|  | 
 | ||||||
|  | 	aliases { | ||||||
|  | 		ethernet0 = &emac; | ||||||
|  | 		serial0 = &uart0; | ||||||
|  | 	}; | ||||||
|  | 
 | ||||||
|  | 	chosen { | ||||||
|  | 		stdout-path = "serial0:115200n8"; | ||||||
|  | 	}; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | &ehci0 { | ||||||
|  | 	status = "okay"; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | &emac { | ||||||
|  | 	pinctrl-names = "default"; | ||||||
|  | 	pinctrl-0 = <&rgmii_pins>; | ||||||
|  | 	phy-mode = "rgmii"; | ||||||
|  | 	phy-handle = <&ext_rgmii_phy>; | ||||||
|  | 	phy-supply = <®_dc1sw>; | ||||||
|  | 	allwinner,tx-delay-ps = <600>; | ||||||
|  | 	status = "okay"; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | &mdio { | ||||||
|  | 	ext_rgmii_phy: ethernet-phy@1 { | ||||||
|  | 		compatible = "ethernet-phy-ieee802.3-c22"; | ||||||
|  | 		reg = <1>; | ||||||
|  | 	}; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | &ohci0 { | ||||||
|  | 	status = "okay"; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | ®_dc1sw { | ||||||
|  | 	regulator-name = "vcc-phy"; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | &uart0 { | ||||||
|  | 	pinctrl-names = "default"; | ||||||
|  | 	pinctrl-0 = <&uart0_pb_pins>; | ||||||
|  | 	status = "okay"; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | &usb_otg { | ||||||
|  | 	dr_mode = "host"; | ||||||
|  | 	status = "okay"; | ||||||
|  | }; | ||||||
|  | 
 | ||||||
|  | &usbphy { | ||||||
|  | 	status = "okay"; | ||||||
|  | }; | ||||||
|  | @ -28,6 +28,8 @@ | ||||||
| #define SUNXI_BOOTED_FROM_NAND	1 | #define SUNXI_BOOTED_FROM_NAND	1 | ||||||
| #define SUNXI_BOOTED_FROM_MMC2	2 | #define SUNXI_BOOTED_FROM_MMC2	2 | ||||||
| #define SUNXI_BOOTED_FROM_SPI	3 | #define SUNXI_BOOTED_FROM_SPI	3 | ||||||
|  | #define SUNXI_BOOTED_FROM_MMC0_HIGH	0x10 | ||||||
|  | #define SUNXI_BOOTED_FROM_MMC2_HIGH	0x12 | ||||||
| 
 | 
 | ||||||
| /* boot head definition from sun4i boot code */ | /* boot head definition from sun4i boot code */ | ||||||
| struct boot_file_head { | struct boot_file_head { | ||||||
|  |  | ||||||
|  | @ -426,10 +426,11 @@ endif | ||||||
| 
 | 
 | ||||||
| config DRAM_ZQ | config DRAM_ZQ | ||||||
| 	int "sunxi dram zq value" | 	int "sunxi dram zq value" | ||||||
| 	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | 	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ | ||||||
|  | 		       MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T | ||||||
| 	default 127 if MACH_SUN7I | 	default 127 if MACH_SUN7I | ||||||
| 	default 14779 if MACH_SUN8I_V3S | 	default 14779 if MACH_SUN8I_V3S | ||||||
| 	default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6 | 	default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6 | ||||||
| 	default 4145117 if MACH_SUN9I | 	default 4145117 if MACH_SUN9I | ||||||
| 	default 3881915 if MACH_SUN50I | 	default 3881915 if MACH_SUN50I | ||||||
| 	---help--- | 	---help--- | ||||||
|  | @ -438,6 +439,7 @@ config DRAM_ZQ | ||||||
| config DRAM_ODT_EN | config DRAM_ODT_EN | ||||||
| 	bool "sunxi dram odt enable" | 	bool "sunxi dram odt enable" | ||||||
| 	default y if MACH_SUN8I_A23 | 	default y if MACH_SUN8I_A23 | ||||||
|  | 	default y if MACH_SUNXI_H3_H5 | ||||||
| 	default y if MACH_SUN8I_R40 | 	default y if MACH_SUN8I_R40 | ||||||
| 	default y if MACH_SUN50I | 	default y if MACH_SUN50I | ||||||
| 	default y if MACH_SUN50I_H6 | 	default y if MACH_SUN50I_H6 | ||||||
|  |  | ||||||
|  | @ -240,10 +240,12 @@ uint32_t sunxi_get_boot_device(void) | ||||||
| 	boot_source = readb(SPL_ADDR + 0x28); | 	boot_source = readb(SPL_ADDR + 0x28); | ||||||
| 	switch (boot_source) { | 	switch (boot_source) { | ||||||
| 	case SUNXI_BOOTED_FROM_MMC0: | 	case SUNXI_BOOTED_FROM_MMC0: | ||||||
|  | 	case SUNXI_BOOTED_FROM_MMC0_HIGH: | ||||||
| 		return BOOT_DEVICE_MMC1; | 		return BOOT_DEVICE_MMC1; | ||||||
| 	case SUNXI_BOOTED_FROM_NAND: | 	case SUNXI_BOOTED_FROM_NAND: | ||||||
| 		return BOOT_DEVICE_NAND; | 		return BOOT_DEVICE_NAND; | ||||||
| 	case SUNXI_BOOTED_FROM_MMC2: | 	case SUNXI_BOOTED_FROM_MMC2: | ||||||
|  | 	case SUNXI_BOOTED_FROM_MMC2_HIGH: | ||||||
| 		return BOOT_DEVICE_MMC2; | 		return BOOT_DEVICE_MMC2; | ||||||
| 	case SUNXI_BOOTED_FROM_SPI: | 	case SUNXI_BOOTED_FROM_SPI: | ||||||
| 		return BOOT_DEVICE_SPI; | 		return BOOT_DEVICE_SPI; | ||||||
|  |  | ||||||
|  | @ -152,7 +152,7 @@ static void auto_set_timing_para(struct dram_para *para) | ||||||
| 	reg_val &= ~(0xff << 8); | 	reg_val &= ~(0xff << 8); | ||||||
| 	reg_val &= ~(0xff << 0); | 	reg_val &= ~(0xff << 0); | ||||||
| 	reg_val |= (0x33 << 8); | 	reg_val |= (0x33 << 8); | ||||||
| 	reg_val |= (0x8 << 0); | 	reg_val |= (0x10 << 0); | ||||||
| 	writel(reg_val, &mctl_ctl->dramtmg8); | 	writel(reg_val, &mctl_ctl->dramtmg8); | ||||||
| 	/* Set phy interface time */ | 	/* Set phy interface time */ | ||||||
| 	reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | 	reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | ||||||
|  |  | ||||||
|  | @ -341,6 +341,11 @@ M:	FUKAUMI Naoki <naobsd@gmail.com> | ||||||
| S:	Maintained | S:	Maintained | ||||||
| F:	configs/Nintendo_NES_Classic_Edition_defconfig | F:	configs/Nintendo_NES_Classic_Edition_defconfig | ||||||
| 
 | 
 | ||||||
|  | OCEANIC 5205 5INMFD BOARD | ||||||
|  | M:	Jagan Teki <jagan@amarulasolutions.com> | ||||||
|  | S:	Maintained | ||||||
|  | F:	configs/oceanic_5205_5inmfd_defconfig | ||||||
|  | 
 | ||||||
| OLIMEX A20-SOM204 BOARD | OLIMEX A20-SOM204 BOARD | ||||||
| M:	Stefan Mavrodiev <stefan@olimex.com> | M:	Stefan Mavrodiev <stefan@olimex.com> | ||||||
| S:	Maintained | S:	Maintained | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MACPWR="PD6" | CONFIG_MACPWR="PD6" | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MACPWR="PD6" | CONFIG_MACPWR="PD6" | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=408 | CONFIG_DRAM_CLK=408 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MMC0_CD_PIN="" | CONFIG_MMC0_CD_PIN="" | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| # CONFIG_CMD_FLASH is not set | # CONFIG_CMD_FLASH is not set | ||||||
|  |  | ||||||
|  | @ -4,6 +4,7 @@ CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=408 | CONFIG_DRAM_CLK=408 | ||||||
| CONFIG_DRAM_ZQ=3881977 | CONFIG_DRAM_ZQ=3881977 | ||||||
|  | # CONFIG_DRAM_ODT_EN is not set | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=408 | CONFIG_DRAM_CLK=408 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| # CONFIG_CMD_FLASH is not set | # CONFIG_CMD_FLASH is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=408 | CONFIG_DRAM_CLK=408 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MMC0_CD_PIN="PH13" | CONFIG_MMC0_CD_PIN="PH13" | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -4,6 +4,7 @@ CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881977 | CONFIG_DRAM_ZQ=3881977 | ||||||
|  | # CONFIG_DRAM_ODT_EN is not set | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| # CONFIG_CMD_FLASH is not set | # CONFIG_CMD_FLASH is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=408 | CONFIG_DRAM_CLK=408 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| # CONFIG_VIDEO_DE2 is not set | # CONFIG_VIDEO_DE2 is not set | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=408 | CONFIG_DRAM_CLK=408 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| # CONFIG_VIDEO_DE2 is not set | # CONFIG_VIDEO_DE2 is not set | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -4,6 +4,7 @@ CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=408 | CONFIG_DRAM_CLK=408 | ||||||
| CONFIG_DRAM_ZQ=3881977 | CONFIG_DRAM_ZQ=3881977 | ||||||
|  | # CONFIG_DRAM_ODT_EN is not set | ||||||
| CONFIG_MACPWR="PD6" | CONFIG_MACPWR="PD6" | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -0,0 +1,20 @@ | ||||||
|  | CONFIG_ARM=y | ||||||
|  | CONFIG_ARCH_SUNXI=y | ||||||
|  | CONFIG_SPL=y | ||||||
|  | CONFIG_MACH_SUN50I=y | ||||||
|  | CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y | ||||||
|  | CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y | ||||||
|  | CONFIG_DRAM_CLK=552 | ||||||
|  | CONFIG_DRAM_ZQ=3881949 | ||||||
|  | CONFIG_MMC0_CD_PIN="" | ||||||
|  | CONFIG_SPL_SPI_SUNXI=y | ||||||
|  | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  | # CONFIG_CMD_FLASH is not set | ||||||
|  | # CONFIG_SPL_DOS_PARTITION is not set | ||||||
|  | # CONFIG_SPL_EFI_PARTITION is not set | ||||||
|  | CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-oceanic-5205-5inmfd" | ||||||
|  | CONFIG_SUN8I_EMAC=y | ||||||
|  | CONFIG_USB_EHCI_HCD=y | ||||||
|  | CONFIG_USB_OHCI_HCD=y | ||||||
|  | CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y | ||||||
|  | @ -4,8 +4,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_USB1_VBUS_PIN="PG13" | CONFIG_USB1_VBUS_PIN="PG13" | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| # CONFIG_CMD_FLASH is not set | # CONFIG_CMD_FLASH is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| # CONFIG_CMD_FLASH is not set | # CONFIG_CMD_FLASH is not set | ||||||
|  |  | ||||||
|  | @ -4,6 +4,7 @@ CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881977 | CONFIG_DRAM_ZQ=3881977 | ||||||
|  | # CONFIG_DRAM_ODT_EN is not set | ||||||
| CONFIG_MACPWR="PD6" | CONFIG_MACPWR="PD6" | ||||||
| CONFIG_SPL_SPI_SUNXI=y | CONFIG_SPL_SPI_SUNXI=y | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=624 | CONFIG_DRAM_CLK=624 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| CONFIG_SPL_I2C_SUPPORT=y | CONFIG_SPL_I2C_SUPPORT=y | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=624 | CONFIG_DRAM_CLK=624 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MACPWR="PD6" | CONFIG_MACPWR="PD6" | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| CONFIG_MACPWR="PD6" | CONFIG_MACPWR="PD6" | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_USB1_VBUS_PIN="PG13" | CONFIG_USB1_VBUS_PIN="PG13" | ||||||
|  |  | ||||||
|  | @ -4,6 +4,7 @@ CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881977 | CONFIG_DRAM_ZQ=3881977 | ||||||
|  | # CONFIG_DRAM_ODT_EN is not set | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| # CONFIG_CMD_FLASH is not set | # CONFIG_CMD_FLASH is not set | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=624 | CONFIG_DRAM_CLK=624 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| # CONFIG_VIDEO_DE2 is not set | # CONFIG_VIDEO_DE2 is not set | ||||||
| CONFIG_SPL_SPI_SUNXI=y | CONFIG_SPL_SPI_SUNXI=y | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y | ||||||
| CONFIG_SPL=y | CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN8I_H3=y | CONFIG_MACH_SUN8I_H3=y | ||||||
| CONFIG_DRAM_CLK=624 | CONFIG_DRAM_CLK=624 | ||||||
| CONFIG_DRAM_ZQ=3881979 |  | ||||||
| CONFIG_DRAM_ODT_EN=y |  | ||||||
| # CONFIG_VIDEO_DE2 is not set | # CONFIG_VIDEO_DE2 is not set | ||||||
| CONFIG_SPL_SPI_SUNXI=y | CONFIG_SPL_SPI_SUNXI=y | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -4,6 +4,7 @@ CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=672 | CONFIG_DRAM_CLK=672 | ||||||
| CONFIG_DRAM_ZQ=3881977 | CONFIG_DRAM_ZQ=3881977 | ||||||
|  | # CONFIG_DRAM_ODT_EN is not set | ||||||
| CONFIG_MMC0_CD_PIN="PH13" | CONFIG_MMC0_CD_PIN="PH13" | ||||||
| CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | CONFIG_MMC_SUNXI_SLOT_EXTRA=2 | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
|  |  | ||||||
|  | @ -4,6 +4,7 @@ CONFIG_SPL=y | ||||||
| CONFIG_MACH_SUN50I_H5=y | CONFIG_MACH_SUN50I_H5=y | ||||||
| CONFIG_DRAM_CLK=624 | CONFIG_DRAM_CLK=624 | ||||||
| CONFIG_DRAM_ZQ=3881977 | CONFIG_DRAM_ZQ=3881977 | ||||||
|  | # CONFIG_DRAM_ODT_EN is not set | ||||||
| CONFIG_NR_DRAM_BANKS=1 | CONFIG_NR_DRAM_BANKS=1 | ||||||
| # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set | ||||||
| # CONFIG_CMD_FLASH is not set | # CONFIG_CMD_FLASH is not set | ||||||
|  |  | ||||||
|  | @ -16,4 +16,5 @@ CONFIG_NR_DRAM_BANKS=1 | ||||||
| CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts" | CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts" | ||||||
| CONFIG_SUN8I_EMAC=y | CONFIG_SUN8I_EMAC=y | ||||||
| CONFIG_USB_EHCI_HCD=y | CONFIG_USB_EHCI_HCD=y | ||||||
|  | CONFIG_USB_OHCI_HCD=y | ||||||
| CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y | CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y | ||||||
|  |  | ||||||
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		Reference in New Issue