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clk: rockchip: rk3399: Fix check patch warnings and checks 

- CHECK: spaces preferred around that '*'
- CHECK: spaces preferred around that '/'
- CHECK: space preferred before that '|'
- WARNING: macros should not use a trailing semicolon
- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'
- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'
- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'
- WARNING: line over 80 characters
- CHECK: Prefer kernel type 'u8' over 'uint8_t'
- Add proper macro definitions arrangements

Note: there are still line over 80 characters and other warnings but
fixing those making code look unreadable, so I kept it as it is.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2019-07-15 23:51:10 +05:30 committed by Kever Yang
parent 7757d1102f
commit dd7dfa217e
1 changed files with 31 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/clk/rockchip/clk_rk3399.c
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@ -38,7 +38,7 @@ struct pll_div {
}; };
#define RATE_TO_DIV(input_rate, output_rate) \ #define RATE_TO_DIV(input_rate, output_rate) \
((input_rate) / (output_rate) - 1); ((input_rate) / (output_rate) - 1)
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
@ -393,7 +393,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
fref_khz = ref_khz / refdiv; fref_khz = ref_khz / refdiv;
fbdiv = vco_khz / fref_khz; fbdiv = vco_khz / fref_khz;
if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
continue; continue;
diff_khz = vco_khz - fbdiv * fref_khz; diff_khz = vco_khz - fbdiv * fref_khz;
if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
@ -489,28 +489,21 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,
} }
#define I2C_CLK_REG_MASK(bus) \ #define I2C_CLK_REG_MASK(bus) \
(I2C_DIV_CON_MASK << \ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
CLK_I2C ##bus## _DIV_CON_SHIFT | \ CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
CLK_I2C_PLL_SEL_MASK << \
CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_REG_VALUE(bus, clk_div) \ #define I2C_CLK_REG_VALUE(bus, clk_div) \
((clk_div - 1) << \ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
CLK_I2C ##bus## _DIV_CON_SHIFT | \ CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
CLK_I2C_PLL_SEL_GPLL << \
CLK_I2C ##bus## _PLL_SEL_SHIFT)
#define I2C_CLK_DIV_VALUE(con, bus) \ #define I2C_CLK_DIV_VALUE(con, bus) \
(con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
I2C_DIV_CON_MASK;
#define I2C_PMUCLK_REG_MASK(bus) \ #define I2C_PMUCLK_REG_MASK(bus) \
(I2C_DIV_CON_MASK << \ (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
CLK_I2C ##bus## _DIV_CON_SHIFT)
#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
((clk_div - 1) << \ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
CLK_I2C ##bus## _DIV_CON_SHIFT)
static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
{ {
@ -597,9 +590,9 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
*/ */
struct spi_clkreg { struct spi_clkreg {
uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ u8 reg; /* CLKSEL_CON[reg] register in CRU */
uint8_t div_shift; u8 div_shift;
uint8_t sel_shift; u8 sel_shift;
}; };
/* /*
@ -916,7 +909,6 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_UART2: case SCLK_UART2:
case SCLK_UART3: case SCLK_UART3:
return 24000000; return 24000000;
break;
case PCLK_HDMI_CTRL: case PCLK_HDMI_CTRL:
break; break;
case DCLK_VOP0: case DCLK_VOP0:
@ -1014,7 +1006,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
return ret; return ret;
} }
static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
struct clk *parent)
{ {
struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
const char *clock_output_name; const char *clock_output_name;
@ -1024,7 +1017,7 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa
* If the requested parent is in the same clock-controller and * If the requested parent is in the same clock-controller and
* the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
*/ */
if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
debug("%s: switching RGMII to SCLK_MAC\n", __func__); debug("%s: switching RGMII to SCLK_MAC\n", __func__);
rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
return 0; return 0;
@ -1049,7 +1042,8 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa
return -EINVAL; return -EINVAL;
} }
static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
struct clk *parent)
{ {
switch (clk->id) { switch (clk->id) {
case SCLK_RMII_SRC: case SCLK_RMII_SRC: