dm: ls1021a: Bring in ls1021a dts files from linux kernel
Bring in required device tree files for ls1021a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
haikun
Simon Glass
parent
b6286a1f54
commit
ddf79f3623
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@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) += \
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socfpga_cyclone5_socdk.dtb \
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socfpga_cyclone5_socrates.dtb
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dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
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ls1021a-twr.dtb
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targets += $(dtb-y)
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DTC_FLAGS += -R 4 -p 0x1000
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@ -0,0 +1,201 @@
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/*
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* Freescale ls1021a QDS board device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "ls1021a.dtsi"
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/ {
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model = "LS1021A QDS Board";
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aliases {
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enet0_rgmii_phy = &rgmii_phy1;
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enet1_rgmii_phy = &rgmii_phy2;
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enet2_rgmii_phy = &rgmii_phy3;
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enet0_sgmii_phy = &sgmii_phy1c;
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enet1_sgmii_phy = &sgmii_phy1d;
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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dspiflash: at45db021d@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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pca9547: mux@77 {
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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ds3232: rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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eeprom@56 {
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compatible = "atmel,24c512";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "atmel,24c512";
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reg = <0x57>;
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};
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adt7461a@4c {
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compatible = "adi,adt7461a";
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reg = <0x4c>;
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};
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};
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000
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0x2 0x0 0x0 0x7e800000 0x00010000
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0x3 0x0 0x0 0x7fb00000 0x00000100>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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fpga: board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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reg = <0x3 0x0 0x0000100>;
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bank-width = <1>;
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device-width = <1>;
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ranges = <0 3 0 0x100>;
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mdio-mux-emi1 {
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compatible = "mdio-mux-mmioreg";
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mdio-parent-bus = <&mdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x54 1>; /* BRDCFG4 */
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mux-mask = <0xe0>; /* EMI1[2:0] */
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/* Onboard PHYs */
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ls1021amdio0: mdio@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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ls1021amdio1: mdio@20 {
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reg = <0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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ls1021amdio2: mdio@40 {
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reg = <0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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};
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ls1021amdio3: mdio@60 {
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reg = <0x60>;
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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};
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ls1021amdio4: mdio@80 {
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reg = <0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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};
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};
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};
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};
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&lpuart0 {
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status = "okay";
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};
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&mdio0 {
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tbi0: tbi-phy@8 {
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reg = <0x8>;
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device_type = "tbi-phy";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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@ -0,0 +1,88 @@
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/*
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* Freescale ls1021a TWR board device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "ls1021a.dtsi"
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/ {
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model = "LS1021A TWR Board";
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aliases {
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enet2_rgmii_phy = &rgmii_phy1;
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enet0_sgmii_phy = &sgmii_phy2;
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enet1_sgmii_phy = &sgmii_phy0;
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};
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};
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&dspi1 {
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bus-num = <0>;
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status = "okay";
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dspiflash: s25fl064k@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25fl064k";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR Flash on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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};
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&lpuart0 {
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status = "okay";
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};
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&mdio0 {
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sgmii_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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tbi1: tbi-phy@1f {
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reg = <0x1f>;
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device_type = "tbi-phy";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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@ -0,0 +1,370 @@
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/*
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* Freescale ls1021a SOC common device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "skeleton64.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,ls1021a";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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serial4 = &lpuart4;
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serial5 = &lpuart5;
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sysclk = &sysclk;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@f00 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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clocks = <&cluster1_clk>;
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};
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cpu@f01 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>;
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clocks = <&cluster1_clk>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "soc";
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interrupt-parent = <&gic>;
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ranges;
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gic: interrupt-controller@1400000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x1401000 0x0 0x1000>,
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<0x0 0x1402000 0x0 0x1000>,
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<0x0 0x1404000 0x0 0x2000>,
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<0x0 0x1406000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcfg: dcfg@1ee0000 {
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compatible = "fsl,ls1021a-dcfg", "syscon";
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reg = <0x0 0x1ee0000 0x0 0x10000>;
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big-endian;
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};
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esdhc: esdhc@1560000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x1560000 0x0 0x10000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <0>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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big-endian;
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bus-width = <4>;
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status = "disabled";
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};
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scfg: scfg@1570000 {
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compatible = "fsl,ls1021a-scfg", "syscon";
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reg = <0x0 0x1570000 0x0 0x10000>;
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big-endian;
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};
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clockgen: clocking@1ee1000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x1ee1000 0x10000>;
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "sysclk";
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};
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cga_pll1: pll@800 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0x800 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "cga-pll1", "cga-pll1-div2",
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"cga-pll1-div4";
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};
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platform_clk: pll@c00 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0xc00 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "platform-clk", "platform-clk-div2";
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};
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cluster1_clk: clk0c0@0 {
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compatible = "fsl,qoriq-core-mux-2.0";
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#clock-cells = <0>;
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reg = <0x0 0x10>;
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clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
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clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
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clock-output-names = "cluster1-clk";
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};
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};
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dspi0: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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spi-num-chipselects = <5>;
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big-endian;
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status = "disabled";
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};
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dspi1: dspi@2110000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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spi-num-chipselects = <5>;
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big-endian;
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status = "disabled";
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};
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i2c0: i2c@2180000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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i2c1: i2c@2190000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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status = "disabled";
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};
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i2c2: i2c@21a0000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&platform_clk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@21c0500 {
|
||||
compatible = "fsl,16550-FIFO64", "ns16550a";
|
||||
reg = <0x0 0x21c0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <0>;
|
||||
fifo-size = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@21c0600 {
|
||||
compatible = "fsl,16550-FIFO64", "ns16550a";
|
||||
reg = <0x0 0x21c0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <0>;
|
||||
fifo-size = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@21d0500 {
|
||||
compatible = "fsl,16550-FIFO64", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <0>;
|
||||
fifo-size = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@21d0600 {
|
||||
compatible = "fsl,16550-FIFO64", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <0>;
|
||||
fifo-size = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sysclk>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog0: watchdog@2ad0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "wdog-en";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
sai1: sai@2b50000 {
|
||||
compatible = "fsl,vf610-sai";
|
||||
reg = <0x0 0x2b50000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "sai";
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 1 47>,
|
||||
<&edma0 1 46>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai2: sai@2b60000 {
|
||||
compatible = "fsl,vf610-sai";
|
||||
reg = <0x0 0x2b60000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&platform_clk 1>;
|
||||
clock-names = "sai";
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 1 45>,
|
||||
<&edma0 1 44>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&platform_clk 1>,
|
||||
<&platform_clk 1>;
|
||||
};
|
||||
|
||||
mdio0: mdio@2d24000 {
|
||||
compatible = "gianfar";
|
||||
device_type = "mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2d24000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb@8600000 {
|
||||
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
|
||||
reg = <0x0 0x8600000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
usb3@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue