socfpga: Adding Clock Manager driver
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
This commit is contained in:
Chin Liang See
Albert ARIBAUD
parent
1a9df13d5b
commit
ddfeb0aaf4
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@ -8,5 +8,5 @@
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#
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obj-y := lowlevel_init.o
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obj-y += misc.o timer.o reset_manager.o system_manager.o
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obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o
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obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
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@ -0,0 +1,361 @@
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock_manager.h>
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static const struct socfpga_clock_manager *clock_manager_base =
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(void *)SOCFPGA_CLKMGR_ADDRESS;
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#define CLKMGR_BYPASS_ENABLE 1
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#define CLKMGR_BYPASS_DISABLE 0
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#define CLKMGR_STAT_IDLE 0
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#define CLKMGR_STAT_BUSY 1
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#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
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#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
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#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
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#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
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#define CLEAR_BGP_EN_PWRDN \
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(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
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CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
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CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
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#define VCO_EN_BASE \
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(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
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CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
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CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
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static inline void cm_wait_for_lock(uint32_t mask)
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{
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register uint32_t inter_val;
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do {
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inter_val = readl(&clock_manager_base->inter) & mask;
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} while (inter_val != mask);
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}
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/* function to poll in the fsm busy bit */
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static inline void cm_wait_for_fsm(void)
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{
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while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
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;
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}
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static inline void cm_write_bypass(uint32_t val)
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{
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writel(val, &clock_manager_base->bypass);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static inline void cm_write_ctrl(uint32_t val)
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{
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writel(val, &clock_manager_base->ctrl);
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cm_wait_for_fsm();
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}
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/* function to write a clock register that has phase information */
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static inline void cm_write_with_phase(uint32_t value,
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uint32_t reg_address, uint32_t mask)
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{
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/* poll until phase is zero */
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while (readl(reg_address) & mask)
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;
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writel(value, reg_address);
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while (readl(reg_address) & mask)
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;
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}
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/*
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* Setup clocks while making no assumptions about previous state of the clocks.
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*
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* Start by being paranoid and gate all sw managed clocks
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* Put all plls in bypass
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* Put all plls VCO registers back to reset value (bandgap power down).
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* Put peripheral and main pll src to reset value to avoid glitch.
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* Delay 5 us.
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* Deassert bandgap power down and set numerator and denominator
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* Start 7 us timer.
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* set internal dividers
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* Wait for 7 us timer.
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* Enable plls
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* Set external dividers while plls are locking
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* Wait for pll lock
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* Assert/deassert outreset all.
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* Take all pll's out of bypass
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* Clear safe mode
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* set source main and peripheral clocks
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* Ungate clocks
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*/
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void cm_basic_init(const cm_config_t *cfg)
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{
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uint32_t start, timeout;
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/* Start by being paranoid and gate all sw managed clocks */
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/*
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* We need to disable nandclk
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* and then do another apb access before disabling
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* gatting off the rest of the periperal clocks.
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*/
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writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
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readl(&clock_manager_base->per_pll_en),
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&clock_manager_base->per_pll_en);
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/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
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writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
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CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
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&clock_manager_base->main_pll_en);
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writel(0, &clock_manager_base->sdr_pll_en);
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/* now we can gate off the rest of the peripheral clocks */
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writel(0, &clock_manager_base->per_pll_en);
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/* Put all plls in bypass */
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cm_write_bypass(
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CLKMGR_BYPASS_PERPLLSRC_SET(
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CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_SDRPLLSRC_SET(
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CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
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CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
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CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
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/*
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* Put all plls VCO registers back to reset value.
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* Some code might have messed with them.
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*/
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writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
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&clock_manager_base->main_pll_vco);
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writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
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&clock_manager_base->per_pll_vco);
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writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
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&clock_manager_base->sdr_pll_vco);
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/*
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* The clocks to the flash devices and the L4_MAIN clocks can
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* glitch when coming out of safe mode if their source values
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* are different from their reset value. So the trick it to
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* put them back to their reset state, and change input
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* after exiting safe mode but before ungating the clocks.
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*/
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writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
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&clock_manager_base->per_pll_src);
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writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
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&clock_manager_base->main_pll_l4src);
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/* read back for the required 5 us delay. */
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readl(&clock_manager_base->main_pll_vco);
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readl(&clock_manager_base->per_pll_vco);
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readl(&clock_manager_base->sdr_pll_vco);
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/*
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* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
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* with numerator and denominator.
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*/
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writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
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CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->main_pll_vco);
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writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
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CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->per_pll_vco);
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writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
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cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
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CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
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&clock_manager_base->sdr_pll_vco);
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/*
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* Time starts here
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* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
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*/
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reset_timer();
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start = get_timer(0);
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/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
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timeout = 7;
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/* main mpu */
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writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk);
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/* main main clock */
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writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk);
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/* main for dbg */
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writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk);
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/* main for cfgs2fuser0clk */
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writel(cfg->cfg2fuser0clk,
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&clock_manager_base->main_pll_cfgs2fuser0clk);
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/* Peri emac0 50 MHz default to RMII */
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writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk);
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/* Peri emac1 50 MHz default to RMII */
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writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk);
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/* Peri QSPI */
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writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk);
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writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk);
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/* Peri pernandsdmmcclk */
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writel(cfg->pernandsdmmcclk,
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&clock_manager_base->per_pll_pernandsdmmcclk);
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/* Peri perbaseclk */
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writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk);
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/* Peri s2fuser1clk */
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writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk);
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/* 7 us must have elapsed before we can enable the VCO */
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while (get_timer(start) < timeout)
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;
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/* Enable vco */
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/* main pll vco */
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writel(cfg->main_vco_base | VCO_EN_BASE,
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&clock_manager_base->main_pll_vco);
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/* periferal pll */
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writel(cfg->peri_vco_base | VCO_EN_BASE,
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&clock_manager_base->per_pll_vco);
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/* sdram pll vco */
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writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
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cfg->sdram_vco_base | VCO_EN_BASE,
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&clock_manager_base->sdr_pll_vco);
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/* L3 MP and L3 SP */
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writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv);
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writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv);
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writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv);
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/* L4 MP, L4 SP, can0, and can1 */
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writel(cfg->perdiv, &clock_manager_base->per_pll_div);
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writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv);
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#define LOCKED_MASK \
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(CLKMGR_INTER_SDRPLLLOCKED_MASK | \
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CLKMGR_INTER_PERPLLLOCKED_MASK | \
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CLKMGR_INTER_MAINPLLLOCKED_MASK)
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cm_wait_for_lock(LOCKED_MASK);
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/* write the sdram clock counters before toggling outreset all */
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writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
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&clock_manager_base->sdr_pll_ddrdqsclk);
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writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
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&clock_manager_base->sdr_pll_ddr2xdqsclk);
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writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
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&clock_manager_base->sdr_pll_ddrdqclk);
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writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
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&clock_manager_base->sdr_pll_s2fuser2clk);
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/*
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* after locking, but before taking out of bypass
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* assert/deassert outresetall
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*/
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uint32_t mainvco = readl(&clock_manager_base->main_pll_vco);
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/* assert main outresetall */
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writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->main_pll_vco);
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uint32_t periphvco = readl(&clock_manager_base->per_pll_vco);
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/* assert pheriph outresetall */
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writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->per_pll_vco);
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/* assert sdram outresetall */
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writel(cfg->sdram_vco_base | VCO_EN_BASE|
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
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&clock_manager_base->sdr_pll_vco);
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/* deassert main outresetall */
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writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->main_pll_vco);
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/* deassert pheriph outresetall */
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writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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&clock_manager_base->per_pll_vco);
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/* deassert sdram outresetall */
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writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
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cfg->sdram_vco_base | VCO_EN_BASE,
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&clock_manager_base->sdr_pll_vco);
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/*
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* now that we've toggled outreset all, all the clocks
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* are aligned nicely; so we can change any phase.
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*/
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cm_write_with_phase(cfg->ddrdqsclk,
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(uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk,
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CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
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/* SDRAM DDR2XDQSCLK */
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cm_write_with_phase(cfg->ddr2xdqsclk,
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(uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk,
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
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cm_write_with_phase(cfg->ddrdqclk,
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(uint32_t)&clock_manager_base->sdr_pll_ddrdqclk,
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CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
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cm_write_with_phase(cfg->s2fuser2clk,
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(uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk,
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
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/* Take all three PLLs out of bypass when safe mode is cleared. */
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cm_write_bypass(
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CLKMGR_BYPASS_PERPLLSRC_SET(
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CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_SDRPLLSRC_SET(
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CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
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CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
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CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
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CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
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/* clear safe mode */
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cm_write_ctrl(readl(&clock_manager_base->ctrl) |
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CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
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/*
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* now that safe mode is clear with clocks gated
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* it safe to change the source mux for the flashes the the L4_MAIN
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*/
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writel(cfg->persrc, &clock_manager_base->per_pll_src);
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writel(cfg->l4src, &clock_manager_base->main_pll_l4src);
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/* Now ungate non-hw-managed clocks */
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writel(~0, &clock_manager_base->main_pll_en);
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writel(~0, &clock_manager_base->per_pll_en);
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writel(~0, &clock_manager_base->sdr_pll_en);
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}
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@ -28,10 +28,99 @@ u32 spl_boot_device(void)
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void spl_board_init(void)
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{
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#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
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cm_config_t cm_default_cfg = {
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/* main group */
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MAIN_VCO_BASE,
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CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
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CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
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CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
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CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
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CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
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CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
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CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
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CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
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CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
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CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
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CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
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CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
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CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
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CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
|
||||
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
|
||||
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
|
||||
CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
|
||||
CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
|
||||
CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
|
||||
CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
|
||||
CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
|
||||
|
||||
/* peripheral group */
|
||||
PERI_VCO_BASE,
|
||||
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
|
||||
CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
|
||||
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
|
||||
CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
|
||||
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
|
||||
CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
|
||||
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
|
||||
CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
|
||||
CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
|
||||
CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
|
||||
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
|
||||
CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
|
||||
CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
|
||||
CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
|
||||
CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
|
||||
CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
|
||||
CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
|
||||
CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
|
||||
CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
|
||||
CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
|
||||
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
|
||||
CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
|
||||
CLKMGR_PERPLLGRP_SRC_QSPI_SET(
|
||||
CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
|
||||
CLKMGR_PERPLLGRP_SRC_NAND_SET(
|
||||
CONFIG_HPS_PERPLLGRP_SRC_NAND) |
|
||||
CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
|
||||
CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
|
||||
|
||||
/* sdram pll group */
|
||||
SDR_VCO_BASE,
|
||||
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
|
||||
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
|
||||
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
|
||||
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
|
||||
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
|
||||
};
|
||||
|
||||
debug("Freezing all I/O banks\n");
|
||||
/* freeze all IO banks */
|
||||
sys_mgr_frzctrl_freeze_req();
|
||||
|
||||
debug("Reconfigure Clock Manager\n");
|
||||
/* reconfigure the PLLs */
|
||||
cm_basic_init(&cm_default_cfg);
|
||||
|
||||
/* configure the pin muxing through system manager */
|
||||
sysmgr_pinmux_init();
|
||||
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,205 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_MANAGER_H_
|
||||
#define _CLOCK_MANAGER_H_
|
||||
|
||||
typedef struct {
|
||||
/* main group */
|
||||
uint32_t main_vco_base;
|
||||
uint32_t mpuclk;
|
||||
uint32_t mainclk;
|
||||
uint32_t dbgatclk;
|
||||
uint32_t mainqspiclk;
|
||||
uint32_t mainnandsdmmcclk;
|
||||
uint32_t cfg2fuser0clk;
|
||||
uint32_t maindiv;
|
||||
uint32_t dbgdiv;
|
||||
uint32_t tracediv;
|
||||
uint32_t l4src;
|
||||
|
||||
/* peripheral group */
|
||||
uint32_t peri_vco_base;
|
||||
uint32_t emac0clk;
|
||||
uint32_t emac1clk;
|
||||
uint32_t perqspiclk;
|
||||
uint32_t pernandsdmmcclk;
|
||||
uint32_t perbaseclk;
|
||||
uint32_t s2fuser1clk;
|
||||
uint32_t perdiv;
|
||||
uint32_t gpiodiv;
|
||||
uint32_t persrc;
|
||||
|
||||
/* sdram pll group */
|
||||
uint32_t sdram_vco_base;
|
||||
uint32_t ddrdqsclk;
|
||||
uint32_t ddr2xdqsclk;
|
||||
uint32_t ddrdqclk;
|
||||
uint32_t s2fuser2clk;
|
||||
} cm_config_t;
|
||||
|
||||
extern void cm_basic_init(const cm_config_t *cfg);
|
||||
|
||||
struct socfpga_clock_manager {
|
||||
u32 ctrl;
|
||||
u32 bypass;
|
||||
u32 inter;
|
||||
u32 intren;
|
||||
u32 dbctrl;
|
||||
u32 stat;
|
||||
u32 _pad_0x18_0x3f[10];
|
||||
u32 mainpllgrp;
|
||||
u32 perpllgrp;
|
||||
u32 sdrpllgrp;
|
||||
u32 _pad_0xe0_0x200[72];
|
||||
|
||||
u32 main_pll_vco;
|
||||
u32 main_pll_misc;
|
||||
u32 main_pll_mpuclk;
|
||||
u32 main_pll_mainclk;
|
||||
u32 main_pll_dbgatclk;
|
||||
u32 main_pll_mainqspiclk;
|
||||
u32 main_pll_mainnandsdmmcclk;
|
||||
u32 main_pll_cfgs2fuser0clk;
|
||||
u32 main_pll_en;
|
||||
u32 main_pll_maindiv;
|
||||
u32 main_pll_dbgdiv;
|
||||
u32 main_pll_tracediv;
|
||||
u32 main_pll_l4src;
|
||||
u32 main_pll_stat;
|
||||
u32 main_pll__pad_0x38_0x40[2];
|
||||
|
||||
u32 per_pll_vco;
|
||||
u32 per_pll_misc;
|
||||
u32 per_pll_emac0clk;
|
||||
u32 per_pll_emac1clk;
|
||||
u32 per_pll_perqspiclk;
|
||||
u32 per_pll_pernandsdmmcclk;
|
||||
u32 per_pll_perbaseclk;
|
||||
u32 per_pll_s2fuser1clk;
|
||||
u32 per_pll_en;
|
||||
u32 per_pll_div;
|
||||
u32 per_pll_gpiodiv;
|
||||
u32 per_pll_src;
|
||||
u32 per_pll_stat;
|
||||
u32 per_pll__pad_0x34_0x40[3];
|
||||
|
||||
u32 sdr_pll_vco;
|
||||
u32 sdr_pll_ctrl;
|
||||
u32 sdr_pll_ddrdqsclk;
|
||||
u32 sdr_pll_ddr2xdqsclk;
|
||||
u32 sdr_pll_ddrdqclk;
|
||||
u32 sdr_pll_s2fuser2clk;
|
||||
u32 sdr_pll_en;
|
||||
u32 sdr_pll_stat;
|
||||
};
|
||||
|
||||
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
|
||||
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
|
||||
#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
|
||||
#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
|
||||
#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
|
||||
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
|
||||
#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
|
||||
#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
|
||||
#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
|
||||
#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
|
||||
#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
|
||||
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \
|
||||
(((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \
|
||||
(((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
|
||||
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
|
||||
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
|
||||
#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
|
||||
#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
|
||||
#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
|
||||
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
|
||||
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
|
||||
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
|
||||
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
|
||||
#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
|
||||
#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
|
||||
#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
|
||||
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
|
||||
#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
|
||||
#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
|
||||
#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
|
||||
#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
|
||||
#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
|
||||
#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
|
||||
#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
|
||||
#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
|
||||
#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
|
||||
#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
|
||||
|
||||
#define MAIN_VCO_BASE \
|
||||
(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
|
||||
CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
|
||||
|
||||
#define PERI_VCO_BASE \
|
||||
(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
|
||||
CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
|
||||
CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
|
||||
|
||||
#define SDR_VCO_BASE \
|
||||
(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
|
||||
CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
|
||||
CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
|
||||
|
||||
#endif /* _CLOCK_MANAGER_H_ */
|
||||
|
|
@ -11,6 +11,7 @@
|
|||
#define SOCFPGA_UART0_ADDRESS 0xffc02000
|
||||
#define SOCFPGA_UART1_ADDRESS 0xffc03000
|
||||
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
|
||||
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
|
||||
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
|
||||
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2014. All rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* This file is generated by Preloader Generator */
|
||||
|
||||
#ifndef _PRELOADER_PLL_CONFIG_H_
|
||||
#define _PRELOADER_PLL_CONFIG_H_
|
||||
|
||||
/* PLL configuration data */
|
||||
/* Main PLL */
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
|
||||
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
|
||||
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
|
||||
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
|
||||
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
|
||||
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
|
||||
/*
|
||||
* To tell where is the clock source:
|
||||
* 0 = MAINPLL
|
||||
* 1 = PERIPHPLL
|
||||
*/
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
|
||||
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
|
||||
|
||||
/* Peripheral PLL */
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
|
||||
/*
|
||||
* To tell where is the VCOs source:
|
||||
* 0 = EOSC1
|
||||
* 1 = EOSC2
|
||||
* 2 = F2S
|
||||
*/
|
||||
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
|
||||
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
|
||||
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
|
||||
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
|
||||
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
|
||||
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
|
||||
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
|
||||
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
|
||||
/*
|
||||
* To tell where is the clock source:
|
||||
* 0 = F2S_PERIPH_REF_CLK
|
||||
* 1 = MAIN_CLK
|
||||
* 2 = PERIPH_CLK
|
||||
*/
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
|
||||
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
|
||||
|
||||
/* SDRAM PLL */
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
|
||||
* This if..else... is not required if generated by tools */
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
|
||||
#else
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
|
||||
/*
|
||||
* To tell where is the VCOs source:
|
||||
* 0 = EOSC1
|
||||
* 1 = EOSC2
|
||||
* 2 = F2S
|
||||
*/
|
||||
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
|
||||
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
|
||||
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
|
||||
|
||||
/* Info for driver */
|
||||
#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
|
||||
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
|
||||
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
|
||||
#else
|
||||
#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
|
||||
#endif
|
||||
#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
|
||||
#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
|
||||
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
|
||||
#define CONFIG_HPS_CLK_NAND_HZ (50000000)
|
||||
#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
|
||||
#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
|
||||
#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
|
||||
#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
|
||||
#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
|
||||
#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
|
||||
#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
|
||||
#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
|
||||
|
||||
#endif /* _PRELOADER_PLL_CONFIG_H_ */
|
||||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include <asm/arch/socfpga_base_addrs.h>
|
||||
#include "../../board/altera/socfpga/pinmux_config.h"
|
||||
#include "../../board/altera/socfpga/pll_config.h"
|
||||
|
||||
/*
|
||||
* High level configuration
|
||||
|
|
|
|||
Loading…
Reference in New Issue