board: ti: am62x: remove rtc setup from spl_board_init()
The am62xxx extended family uses the same 32k crystal for all of its starter kits. Move this to the common board directory to avoid repeating this everywhere. Signed-off-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
parent
851aa09d1e
commit
dee6f6f1c2
|
|
@ -126,13 +126,6 @@ static int video_setup(void)
|
||||||
#define CTRLMMR_USB1_PHY_CTRL 0x43004018
|
#define CTRLMMR_USB1_PHY_CTRL 0x43004018
|
||||||
#define CORE_VOLTAGE 0x80000000
|
#define CORE_VOLTAGE 0x80000000
|
||||||
|
|
||||||
#define WKUP_CTRLMMR_DBOUNCE_CFG1 0x04504084
|
|
||||||
#define WKUP_CTRLMMR_DBOUNCE_CFG2 0x04504088
|
|
||||||
#define WKUP_CTRLMMR_DBOUNCE_CFG3 0x0450408c
|
|
||||||
#define WKUP_CTRLMMR_DBOUNCE_CFG4 0x04504090
|
|
||||||
#define WKUP_CTRLMMR_DBOUNCE_CFG5 0x04504094
|
|
||||||
#define WKUP_CTRLMMR_DBOUNCE_CFG6 0x04504098
|
|
||||||
|
|
||||||
void spl_board_init(void)
|
void spl_board_init(void)
|
||||||
{
|
{
|
||||||
u32 val;
|
u32 val;
|
||||||
|
|
@ -147,29 +140,6 @@ void spl_board_init(void)
|
||||||
val &= ~(CORE_VOLTAGE);
|
val &= ~(CORE_VOLTAGE);
|
||||||
writel(val, CTRLMMR_USB1_PHY_CTRL);
|
writel(val, CTRLMMR_USB1_PHY_CTRL);
|
||||||
|
|
||||||
/* We have 32k crystal, so lets enable it */
|
|
||||||
val = readl(MCU_CTRL_LFXOSC_CTRL);
|
|
||||||
val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
|
|
||||||
writel(val, MCU_CTRL_LFXOSC_CTRL);
|
|
||||||
/* Add any TRIM needed for the crystal here.. */
|
|
||||||
/* Make sure to mux up to take the SoC 32k from the crystal */
|
|
||||||
writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
|
|
||||||
MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
|
|
||||||
|
|
||||||
/* Setup debounce conf registers - arbitrary values. Times are approx */
|
|
||||||
/* 1.9ms debounce @ 32k */
|
|
||||||
writel(WKUP_CTRLMMR_DBOUNCE_CFG1, 0x1);
|
|
||||||
/* 5ms debounce @ 32k */
|
|
||||||
writel(WKUP_CTRLMMR_DBOUNCE_CFG2, 0x5);
|
|
||||||
/* 20ms debounce @ 32k */
|
|
||||||
writel(WKUP_CTRLMMR_DBOUNCE_CFG3, 0x14);
|
|
||||||
/* 46ms debounce @ 32k */
|
|
||||||
writel(WKUP_CTRLMMR_DBOUNCE_CFG4, 0x18);
|
|
||||||
/* 100ms debounce @ 32k */
|
|
||||||
writel(WKUP_CTRLMMR_DBOUNCE_CFG5, 0x1c);
|
|
||||||
/* 156ms debounce @ 32k */
|
|
||||||
writel(WKUP_CTRLMMR_DBOUNCE_CFG6, 0x1f);
|
|
||||||
|
|
||||||
video_setup();
|
video_setup();
|
||||||
enable_caches();
|
enable_caches();
|
||||||
if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP))
|
if (IS_ENABLED(CONFIG_SPL_SPLASH_SCREEN) && IS_ENABLED(CONFIG_SPL_BMP))
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue