ARM: MediaTek: Add support for MT8516 SoC
Add support for MediaTek MT8516 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Fabien Parent
Tom Rini
parent
6fdb50c098
commit
def2fc05f6
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@ -0,0 +1,25 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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&infracfg {
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u-boot,dm-pre-reloc;
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};
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&topckgen_ {
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u-boot,dm-pre-reloc;
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};
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&topckgen_cg {
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u-boot,dm-pre-reloc;
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};
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&apmixedsys {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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#include <dt-bindings/clock/mt8516-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt8516";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt8516-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0>;
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clock-frequency = <1300000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x1>;
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clock-frequency = <1300000000>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x2>;
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clock-frequency = <1300000000>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x3>;
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clock-frequency = <1300000000>;
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};
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};
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt8516-topckgen";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen_cg: clock-controller-cg@10000000 {
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compatible = "mediatek,mt8516-topckgen-cg";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt8516-infracfg";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: clock-controller@10018000 {
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compatible = "mediatek,mt8516-apmixedsys";
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reg = <0x10018000 0x710>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10310000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10200620 0x20>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,wdt";
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reg = <0x10007000 0x1000>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
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#reset-cells = <1>;
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status = "disabled";
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};
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pinctrl: pinctrl@10005000 {
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compatible = "mediatek,mt8516-pinctrl";
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reg = <0x10005000 0x1000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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mmc0: mmc@11120000 {
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compatible = "mediatek,mt8516-mmc";
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reg = <0x11120000 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen_cg CLK_TOP_MSDC0>,
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<&topckgen CLK_TOP_AHB_INFRA_SEL>,
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<&topckgen_cg CLK_TOP_MSDC0_INFRA>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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uart0: serial@11005000 {
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compatible = "mediatek,hsuart";
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reg = <0x11005000 0x1000>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART0_SEL>,
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<&topckgen_cg CLK_TOP_UART0>;
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clock-names = "baud","bus";
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status = "disabled";
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};
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};
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@ -31,6 +31,16 @@ config TARGET_MT7629
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including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
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switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
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config TARGET_MT8516
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bool "MediaTek MT8516 SoC"
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select ARM64
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select ARCH_MISC_INIT
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help
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The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35.
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including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
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Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
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chip and several DDR3 and DDR4 options.
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endchoice
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source "board/mediatek/mt7623/Kconfig"
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@ -5,3 +5,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_TARGET_MT7623) += mt7623/
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obj-$(CONFIG_TARGET_MT7629) += mt7629/
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obj-$(CONFIG_TARGET_MT8516) += mt8516/
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += init.o
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@ -0,0 +1,120 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <ram.h>
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#include <asm/arch/misc.h>
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#include <asm/armv8/mmu.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <linux/io.h>
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#include <dt-bindings/clock/mt8516-clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define WDOG_SWRST 0x10007014
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#define WDOG_SWRST_KEY 0x1209
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int dram_init(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = gd->ram_base;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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int mtk_pll_early_init(void)
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{
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unsigned long pll_rates[] = {
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[CLK_APMIXED_ARMPLL] = 1300000000,
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[CLK_APMIXED_MAINPLL] = 1501000000,
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[CLK_APMIXED_UNIVPLL] = 1248000000,
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[CLK_APMIXED_MMPLL] = 380000000,
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};
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struct udevice *dev;
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int ret, i;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
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if (ret)
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return ret;
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/* configure default rate then enable apmixedsys */
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for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
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struct clk clk = { .id = i, .dev = dev };
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ret = clk_set_rate(&clk, pll_rates[i]);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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}
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return 0;
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}
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int mtk_soc_early_init(void)
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{
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int ret;
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/* initialize early clocks */
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ret = mtk_pll_early_init();
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if (ret)
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return ret;
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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while (1) {
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writel(WDOG_SWRST_KEY, WDOG_SWRST);
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mdelay(5);
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}
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}
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int print_cpuinfo(void)
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{
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printf("CPU: MediaTek MT8516\n");
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return 0;
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}
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static struct mm_region mt8516_mem_map[] = {
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{
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/* DDR */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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}, {
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = mt8516_mem_map;
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