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powerpc/t4qds: Add SW7[4] in the DIP switch display 

SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun 2013-03-25 07:40:14 +00:00 committed by Andy Fleming
parent 16d88f415a
commit e1379b0730
1 changed files with 3 additions and 2 deletions
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5
board/freescale/t4qds/t4qds.c
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@ -801,7 +801,7 @@ void qixis_dump_switch(void)
* Any bit with 1 means that bit cannot be reverse engineered. * Any bit with 1 means that bit cannot be reverse engineered.
* It will be displayed as _ in binary format. * It will be displayed as _ in binary format.
*/ */
static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f}; static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
char buf[10]; char buf[10];
u8 brdcfg[16], dutcfg[16]; u8 brdcfg[16], dutcfg[16];
@ -832,7 +832,8 @@ void qixis_dump_switch(void)
sw[5] = ((brdcfg[0] & 0x0f) << 4) | \ sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \ ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
((brdcfg[0] & 0x40) >> 5); ((brdcfg[0] & 0x40) >> 5);
sw[6] = (brdcfg[11] & 0x20); sw[6] = (brdcfg[11] & 0x20) |
((brdcfg[5] & 0x02) << 3);
sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \ sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
((brdcfg[5] & 0x10) << 2); ((brdcfg[5] & 0x10) << 2);
sw[8] = ((brdcfg[12] & 0x08) << 4) | \ sw[8] = ((brdcfg[12] & 0x08) << 4) | \