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xilinx: r5: Fix MPU setting for R5 

Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a776 ("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek 2020-09-14 16:33:46 +02:00
parent b76907ef90
commit e3259a700a
1 changed files with 4 additions and 7 deletions
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11
arch/arm/mach-zynqmp-r5/cpu.c
View File

@ -11,11 +11,9 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
struct mpu_region_config region_config[] = { struct mpu_region_config region_config[] = {
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_1GB }, SHARED_WRITE_BUFFERED, REGION_4GB },
{ 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO, { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_512MB },
{ 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
O_I_WB_RD_WR_ALLOC, REGION_1GB }, O_I_WB_RD_WR_ALLOC, REGION_1GB },
}; };
@ -23,8 +21,7 @@ int arch_cpu_init(void)
{ {
gd->cpu_clk = CONFIG_CPU_FREQ_HZ; gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
setup_mpu_regions(region_config, sizeof(region_config) / setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
sizeof(struct mpu_region_config));
return 0; return 0;
} }