From e46b2925fcc26b20caec06bbefcfcbcf9dcc0a8c Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Tue, 5 Jul 2022 10:27:26 -0500 Subject: [PATCH] Revert "spi: cadence-qspi: Fix PHY calibration for SPL" This reverts commit 2ad56641d2b73e8f5378419a8803f81acd1884a7. It causes a build break for at least am65x_hs_evm_r5_defconfig, due to SPL size exceeding limits. Revert it till we can fix cleanly. Signed-off-by: Anand Gadiyar --- drivers/spi/cadence_qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index a839c8d2a2..81dd80c389 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -893,7 +893,7 @@ static void cadence_spi_mem_do_calibration(struct spi_slave *spi, struct cadence_spi_platdata *plat = bus->platdata; int ret; - if (!IS_ENABLED(CONFIG_CADENCE_QSPI_PHY) || !plat->has_phy) + if (!CONFIG_IS_ENABLED(CADENCE_QSPI_PHY) || !plat->has_phy) return; plat->phy_read_op = *op;