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serial: uartlite: Fix uninitialized ret in debug uartlite 

Endianness detection is checked against uninitialized ret variable.
Assign ret with read value from status register to fix this.

Fixes: 31a359f87e ("serial: uartlite: Add support to work with any endianness")
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ashok Reddy Soma 2020-12-01 00:34:47 -07:00 committed by Michal Simek
parent d91a652cfd
commit e5e8bbd25a
1 changed files with 1 additions and 1 deletions
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2
drivers/serial/serial_xuartlite.c
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@ -148,7 +148,7 @@ static inline void _debug_uart_init(void)
uart_out32(&regs->control, 0); uart_out32(&regs->control, 0);
uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
uart_in32(&regs->status); ret = uart_in32(&regs->status);
/* Endianness detection */ /* Endianness detection */
if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) { if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
little_endian = true; little_endian = true;