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MLK-18153-1 dts: mx6slevk: Update DTS and DTSi to align with v2017.03 

Copy the DTS and DTSi from v2017.03 u-boot.

Changes in DTS specified for u-boot:
1. Add alias for mmc and usb
2. Add pin settings for i2c bus force idle
3. Remove MMC alias

Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li 2018-04-03 01:49:54 -07:00
parent 779b3bd0ed
commit e669373fc5
2 changed files with 508 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

356
arch/arm/dts/imx6sl-evk.dts
View File

@ -16,6 +16,19 @@
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
battery: max8903@0 {
compatible = "fsl,max8903-charger";
pinctrl-names = "default";
dok_input = <&gpio4 13 1>;
uok_input = <&gpio4 13 1>;
chg_input = <&gpio4 15 1>;
flt_input = <&gpio4 14 1>;
fsl,dcm_always_high;
fsl,dc_valid;
fsl,adc_disable;
status = "okay";
};
memory {
reg = <0x80000000 0x40000000>;
};
@ -39,6 +52,11 @@
};
};
pxp_v4l2_out {
compatible = "fsl,imx6sl-pxp-v4l2";
status = "okay";
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@ -96,7 +114,7 @@
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
cpu-dai = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
@ -107,6 +125,23 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
codec-master;
hp-det-gpios = <&gpio4 19 1>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif",
"fsl,imx6sl-evk-spdif";
model = "imx-spdif";
spdif-controller = <&spdif>;
spdif-out;
};
sii902x_reset: sii902x-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio2 19 1>;
reset-delay-us = <100000>;
#reset-cells = <0>;
};
};
@ -116,7 +151,21 @@
status = "okay";
};
&cpu0 {
arm-supply = <&sw1a_reg>;
soc-supply = <&sw1c_reg>;
};
&csi {
port {
csi_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 11 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
@ -131,6 +180,15 @@
};
};
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_0>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
status = "okay";
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
@ -139,10 +197,17 @@
status = "okay";
};
&gpc {
fsl,ldo-bypass = <1>;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: pfuze100@08 {
@ -244,12 +309,98 @@
};
};
};
elan@10 {
compatible = "elan,elan-touch";
reg = <0x10>;
interrupt-parent = <&gpio2>;
interrupts = <10 2>;
gpio_elan_cs = <&gpio2 9 0>;
gpio_elan_rst = <&gpio4 4 0>;
gpio_intr = <&gpio2 10 0>;
status = "okay";
};
mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
max17135@48 {
compatible = "maxim,max17135";
reg = <0x48>;
vneg_pwrup = <1>;
gvee_pwrup = <2>;
vpos_pwrup = <10>;
gvdd_pwrup = <12>;
gvdd_pwrdn = <1>;
vpos_pwrdn = <2>;
gvee_pwrdn = <8>;
vneg_pwrdn = <10>;
gpio_pmic_pwrgood = <&gpio2 13 0>;
gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
gpio_pmic_wakeup = <&gpio2 14 0>;
gpio_pmic_v3p3 = <&gpio2 7 0>;
gpio_pmic_intr = <&gpio2 12 0>;
regulators {
DISPLAY_reg: DISPLAY {
regulator-name = "DISPLAY";
};
GVDD_reg: GVDD {
/* 20v */
regulator-name = "GVDD";
};
GVEE_reg: GVEE {
/* -22v */
regulator-name = "GVEE";
};
HVINN_reg: HVINN {
/* -22v */
regulator-name = "HVINN";
};
HVINP_reg: HVINP {
/* 20v */
regulator-name = "HVINP";
};
VCOM_reg: VCOM {
regulator-name = "VCOM";
/* 2's-compliment, -4325000 */
regulator-min-microvolt = <0xffbe0178>;
/* 2's-compliment, -500000 */
regulator-max-microvolt = <0xfff85ee0>;
};
VNEG_reg: VNEG {
/* -15v */
regulator-name = "VNEG";
};
VPOS_reg: VPOS {
/* 15v */
regulator-name = "VPOS";
};
V3P3_reg: V3P3 {
regulator-name = "V3P3";
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
status = "okay";
codec: wm8962@1a {
@ -264,6 +415,45 @@
PLLVDD-supply = <&vgen3_reg>;
SPKVDD1-supply = <&reg_aud4v>;
SPKVDD2-supply = <&reg_aud4v>;
amic-mono;
};
sii902x@39 {
compatible = "SiI,sii902x";
interrupt-parent = <&gpio2>;
interrupts = <10 2>;
mode_str ="1280x720M@60";
bits-per-pixel = <16>;
resets = <&sii902x_reset>;
reg = <0x39>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "disabled";
ov5640: ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi_0>;
clocks = <&clks IMX6SL_CLK_CSI>;
clock-names = "csi_mclk";
AVDD-supply = <&vgen6_reg>; /* 2.8v */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
pwn-gpios = <&gpio1 25 1>;
rst-gpios = <&gpio1 26 0>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
port {
ov5640_ep: endpoint {
remote-endpoint = <&csi_ep>;
};
};
};
};
@ -282,6 +472,17 @@
MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000
MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0
MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
>;
};
@ -303,6 +504,39 @@
>;
};
pinctrl_epdc_0: epdcgrp-0 {
fsl,pins = <
MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000
MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000
MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000
MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000
MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000
MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000
MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000
MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000
MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000
MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000
MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000
MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000
MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000
MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000
MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000
MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000
MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
@ -337,6 +571,12 @@
>;
};
pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1
MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
@ -345,6 +585,20 @@
>;
};
pinctrl_i2c2_gpio: i2c2grp_gpio {
fsl,pins = <
MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x1b8b1
MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x1b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
@ -356,7 +610,7 @@
>;
};
pinctrl_lcd: lcdgrp {
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
@ -382,6 +636,11 @@
MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
@ -401,6 +660,12 @@
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
@ -408,6 +673,24 @@
>;
};
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1
MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1
>;
};
pinctrl_uart4dte_1: uart4dtegrp-1 {
fsl,pins = <
MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1
MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1
MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
@ -524,9 +807,34 @@
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
>;
};
pinctrl_csi_0: csigrp-0 {
fsl,pins = <
MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0
MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0
MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0
MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0
MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0
MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0
MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0
MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0
MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0
MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0
MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0
MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
>;
};
};
};
&pxp {
status = "okay";
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
@ -545,13 +853,14 @@
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
display = <&display>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
display: display {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
@ -585,7 +894,21 @@
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif>;
assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>,
<&clks IMX6SL_CLK_SPDIF0_PODF>;
assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>;
assigned-clock-rates = <0>, <227368421>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>,
<&clks IMX6SL_CLK_SSI2>;
assigned-clock-rates = <0>, <24000000>;
status = "okay";
};
@ -600,6 +923,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
disable-over-current;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
@ -610,6 +936,14 @@
status = "okay";
};
&usbphy1 {
tx-d-cal = <0x5>;
};
&usbphy2 {
tx-d-cal = <0x5>;
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -618,6 +952,8 @@
bus-width = <8>;
cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
@ -628,6 +964,8 @@
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
@ -637,5 +975,7 @@
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};

242
arch/arm/dts/imx6sl.dtsi
View File

@ -1,5 +1,5 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2013-2016 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -8,6 +8,8 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
@ -41,13 +43,14 @@
spi3 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
usb0 = &usbotg1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
@ -65,17 +68,37 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>;
clocks = <&clks IMX6SL_CLK_ARM>,
<&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>,
<&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>,
<&clks IMX6SL_CLK_PLL1>,
<&clks IMX6SL_PLL1_BYPASS>,
<&clks IMX6SL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
"pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
"pll1_bypass_src";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x14000000>;
linux,cma-default;
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@ -102,6 +125,10 @@
};
};
reg_vbus_wakeup: usb_vbus_wakeup {
compatible = "fsl,imx6-dummy-ldo2p5";
};
soc {
#address-cells = <1>;
#size-cells = <1>;
@ -109,9 +136,42 @@
interrupt-parent = <&gpc>;
ranges;
ocram: sram@00900000 {
busfreq { /* BUSFREQ */
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
<&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
<&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>,
<&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
<&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
<&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>,
<&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
<&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>,
<&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>,
<&clks IMX6SL_PLL1_BYPASS_SRC>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb",
"ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src",
"pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src";
fsl,max_ddr_freq = <400000000>;
};
ocrams: sram@00900000 {
compatible = "fsl,lpm-sram";
reg = <0x00900000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
ocrams_ddr: sram@00904000 {
compatible = "fsl,ddr-lpm-sram";
reg = <0x00904000 0x1000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
ocram: sram@00905000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
reg = <0x00905000 0x1B000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
@ -150,7 +210,7 @@
reg = <0x02004000 0x4000>;
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 14 18 0>,
<&sdma 15 18 0>;
<&sdma 15 18 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
<&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
@ -161,7 +221,7 @@
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
"rxtx7", "dma";
status = "disabled";
};
@ -174,6 +234,8 @@
clocks = <&clks IMX6SL_CLK_ECSPI1>,
<&clks IMX6SL_CLK_ECSPI1>;
clock-names = "ipg", "per";
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -186,6 +248,8 @@
clocks = <&clks IMX6SL_CLK_ECSPI2>,
<&clks IMX6SL_CLK_ECSPI2>;
clock-names = "ipg", "per";
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -198,6 +262,8 @@
clocks = <&clks IMX6SL_CLK_ECSPI3>,
<&clks IMX6SL_CLK_ECSPI3>;
clock-names = "ipg", "per";
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -210,6 +276,8 @@
clocks = <&clks IMX6SL_CLK_ECSPI4>,
<&clks IMX6SL_CLK_ECSPI4>;
clock-names = "ipg", "per";
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -261,8 +329,8 @@
clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
<&clks IMX6SL_CLK_SSI1>;
clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>,
<&sdma 38 1 0>;
dmas = <&sdma 37 22 0>,
<&sdma 38 22 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
@ -277,8 +345,8 @@
clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
<&clks IMX6SL_CLK_SSI2>;
clock-names = "ipg", "baud";
dmas = <&sdma 41 1 0>,
<&sdma 42 1 0>;
dmas = <&sdma 41 22 0>,
<&sdma 42 22 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
@ -293,8 +361,8 @@
clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
<&clks IMX6SL_CLK_SSI3>;
clock-names = "ipg", "baud";
dmas = <&sdma 45 1 0>,
<&sdma 46 1 0>;
dmas = <&sdma 45 22 0>,
<&sdma 46 22 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
@ -385,12 +453,6 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
<&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
<&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
<&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
<&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
<&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
};
gpio2: gpio@020a0000 {
@ -402,13 +464,6 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
<&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
<&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
<&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
<&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
<&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
<&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
};
gpio3: gpio@020a4000 {
@ -420,14 +475,6 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
<&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
<&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
<&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
<&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
<&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
<&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
<&iomuxc 31 102 1>;
};
gpio4: gpio@020a8000 {
@ -439,21 +486,6 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
<&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
<&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
<&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
<&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
<&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
<&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
<&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
<&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
<&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
<&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
<&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
<&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
<&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
<&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
};
gpio5: gpio@020ac000 {
@ -465,17 +497,6 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
<&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
<&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
<&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
<&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
<&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
<&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
<&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
<&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
<&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
<&iomuxc 21 161 1>;
};
kpp: kpp@020b8000 {
@ -518,7 +539,7 @@
<0 54 IRQ_TYPE_LEVEL_HIGH>,
<0 127 IRQ_TYPE_LEVEL_HIGH>;
regulator-1p1 {
regulator-1p1@110 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
@ -530,23 +551,24 @@
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
anatop-enable-bit = <0>;
};
regulator-3p0 {
reg_3p0: regulator-3p0@120 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
regulator-min-microvolt = <2625000>;
regulator-max-microvolt = <3400000>;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
regulator-2p5 {
regulator-2p5@130 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
@ -558,9 +580,10 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2850000>;
anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
reg_arm: regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddarm";
regulator-min-microvolt = <725000>;
@ -575,14 +598,16 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
reg_pu: regulator-vddpu {
reg_pu: regulator-vddpu@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-enable-ramp-delay = <150>;
regulator-boot-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
@ -592,9 +617,10 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
reg_soc: regulator-vddsoc {
reg_soc: regulator-vddsoc@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
@ -609,6 +635,7 @@
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
regulator-allow-bypass;
};
};
@ -625,6 +652,7 @@
reg = <0x020c9000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBPHY1>;
phy-3p0-supply = <&reg_3p0>;
fsl,anatop = <&anatop>;
};
@ -633,9 +661,16 @@
reg = <0x020ca000 0x1000>;
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBPHY2>;
phy-3p0-supply = <&reg_3p0>;
fsl,anatop = <&anatop>;
};
usbphy_nop1: usbphy_nop1 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX6SL_CLK_USBPHY1>;
clock-names = "main_clk";
};
snvs: snvs@020cc000 {
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
reg = <0x020cc000 0x4000>;
@ -652,7 +687,7 @@
compatible = "syscon-poweroff";
regmap = <&snvs>;
offset = <0x38>;
mask = <0x60>;
mask = <0x61>;
status = "disabled";
};
};
@ -683,8 +718,12 @@
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
<&clks IMX6SL_CLK_GPU2D_PODF>;
clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>,
<&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>,
<&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>,
<&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>;
clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi",
"lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi";
#power-domain-cells = <1>;
};
@ -700,8 +739,14 @@
};
csi: csi@020e4000 {
compatible = "fsl,imx6sl-csi";
reg = <0x020e4000 0x4000>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>,
<&clks IMX6SL_CLK_DUMMY>,
<&clks IMX6SL_CLK_DUMMY>;
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
status = "disabled";
};
spdc: spdc@020e8000 {
@ -717,18 +762,26 @@
<&clks IMX6SL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
iram = <&ocram>;
/* imx6sl reuses imx6q sdma firmware */
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
pxp: pxp@020f0000 {
compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
epdc: epdc@020f4000 {
compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>;
clock-names = "epdc_axi", "epdc_pix";
};
lcdif: lcdif@020f8000 {
@ -743,11 +796,15 @@
};
dcp: dcp@020fc000 {
compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
compatible = "fsl,imx6sl-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
<0 100 IRQ_TYPE_LEVEL_HIGH>,
<0 101 IRQ_TYPE_LEVEL_HIGH>;
/* DCP clock always on */
clocks = <&clks IMX6SL_CLK_DUMMY>;
clock-names = "dcp";
status = "okay";
};
};
@ -768,6 +825,7 @@
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
fsl,anatop = <&anatop>;
status = "disabled";
};
@ -794,6 +852,9 @@
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
phy_type = "hsic";
fsl,usbphy = <&usbphy_nop1>;
fsl,anatop = <&anatop>;
status = "disabled";
};
@ -802,6 +863,7 @@
compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
vbus-wakeup-supply = <&reg_vbus_wakeup>;
};
fec: ethernet@02188000 {
@ -897,18 +959,16 @@
reg = <0x021b0000 0x4000>;
};
rngb: rngb@021b4000 {
rng: rng@021b4000 {
compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
reg = <0x021b4000 0x4000>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
weim: weim@021b8000 {
#address-cells = <2>;
#size-cells = <1>;
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
fsl,weim-cs-gpr = <&gpr>;
status = "disabled";
};
ocotp: ocotp@021bc000 {
@ -922,6 +982,24 @@
reg = <0x021d8000 0x4000>;
status = "disabled";
};
gpu: gpu@02200000 {
compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
<0x80000000 0x0>, <0x0 0x8000000>;
reg-names = "iobase_2d", "iobase_vg",
"phys_baseaddr", "contiguous_mem";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_2d", "irq_vg";
clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
<&clks IMX6SL_CLK_MMDC_ROOT>,
<&clks IMX6SL_CLK_GPU2D_OVG>;
clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
"gpu2d_clk";
resets = <&src 3>, <&src 3>;
reset-names = "gpu2d", "gpuvg";
power-domains = <&gpc 1>;
};
};
};
};