MLK-18152-2 mx6sxsabresd: Update board codes to align with v2017.03
Add emmc support which needs board rework. Add I2C2. Update DM PMIC settings and LDO bypass support. Add BMODE support. Add LVDS and LCD splash screen support Add PCI power and reset GPIO and disable PCI at default. Update QSPI settings for QSPI boot and M4 fastup. Update environment settings Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li
parent
9d8838cb14
commit
e74716b6e7
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@ -9,4 +9,9 @@ config SYS_VENDOR
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config SYS_CONFIG_NAME
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default "mx6sxsabresd"
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config MX6SXSABRESD_EMMC_REWORK
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bool "Select for the board with eMMC rework"
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config SYS_TEXT_BASE
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default 0x87800000
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endif
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -16,7 +16,20 @@ IMAGE_VERSION 2
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* spi/sd/nand/onenand, qspi/nor
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*/
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#ifdef CONFIG_QSPI_BOOT
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BOOT_FROM qspi
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#else
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BOOT_FROM sd
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#endif
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx6sxsabresd/plugin.bin 0x00907000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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@ -130,3 +143,4 @@ DATA 4 0x021b001c 0x04008040
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DATA 4 0x021b0020 0x00000800
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DATA 4 0x021b0818 0x00011117
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DATA 4 0x021b001c 0x00000000
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#endif
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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@ -14,6 +15,7 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/io.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <linux/sizes.h>
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@ -26,7 +28,14 @@
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include "../common/pfuze.h"
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include <asm/mach-imx/video.h>
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#ifdef CONFIG_IMX_RDC
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#include <asm/mach-imx/rdc-sema.h>
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#include <asm/arch/imx-rdc.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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@ -37,6 +46,11 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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@ -47,12 +61,21 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
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#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm)
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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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@ -65,6 +88,60 @@ static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD pin */
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MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* RST_B, used for power reset cycle */
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MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
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static iomux_v3_cfg_t const usdhc4_emmc_pads[] = {
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MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#else
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#endif
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static iomux_v3_cfg_t const wdog_b_pad = {
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MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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@ -85,6 +162,23 @@ static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static iomux_v3_cfg_t const fec2_pads[] = {
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MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static iomux_v3_cfg_t const peri_3v3_pads[] = {
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MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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@ -100,21 +194,39 @@ static iomux_v3_cfg_t const phy_control_pads[] = {
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MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#ifdef CONFIG_PCIE_IMX
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iomux_v3_cfg_t const pcie_pads[] = {
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MX6_PAD_ENET1_COL__GPIO2_IO_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
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MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
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};
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static void setup_pcie(void)
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{
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imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");
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gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");
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}
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static int setup_fec(void)
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static int setup_fec(int fec_id)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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int reg, ret;
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/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
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if (0 == fec_id)
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/* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
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else
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/* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
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ret = enable_fec_anatop_clock(0, ENET_125MHZ);
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ret = enable_fec_anatop_clock(fec_id, ENET_125MHZ);
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if (ret)
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return ret;
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@ -122,11 +234,11 @@ static int setup_fec(void)
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ARRAY_SIZE(phy_control_pads));
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/* Enable the ENET power, active low */
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gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
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gpio_request(IMX_GPIO_NR(2, 6), "fec power en");
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gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
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/* Reset AR8031 PHY */
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gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
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gpio_request(IMX_GPIO_NR(2, 7), "ar8031 reset");
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gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
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mdelay(10);
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gpio_set_value(IMX_GPIO_NR(2, 7), 1);
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@ -140,12 +252,93 @@ static int setup_fec(void)
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int board_eth_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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setup_fec();
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if (0 == CONFIG_FEC_ENET_DEV)
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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else
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imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
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return cpu_eth_init(bis);
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}
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#ifdef CONFIG_SYS_I2C
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
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.gp = IMX_GPIO_NR(1, 0),
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
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.gp = IMX_GPIO_NR(1, 1),
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},
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};
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/* I2C2 */
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
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.gp = IMX_GPIO_NR(1, 2),
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
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.gp = IMX_GPIO_NR(1, 3),
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},
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};
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#endif
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#ifdef CONFIG_POWER
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int power_init_board(void)
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{
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struct pmic *pfuze;
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unsigned int reg;
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int ret;
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pfuze = pfuze_common_init(I2C_PMIC);
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if (!pfuze)
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return -ENODEV;
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ret = pfuze_mode_init(pfuze, APS_PFM);
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if (ret < 0)
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return ret;
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/* set SW1AB standby volatage 1.10V */
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pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®);
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reg &= ~0x3f;
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reg |= PFUZE100_SW1ABC_SETP(11000);
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pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
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/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®);
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reg &= ~0xc0;
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reg |= 0x40;
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pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
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/* set SW1C standby volatage 1.10V */
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pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®);
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reg &= ~0x3f;
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reg |= PFUZE100_SW1ABC_SETP(11000);
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pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
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/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
|
||||
|
||||
/* Enable power of VGEN5 3V3, needed for SD3 */
|
||||
pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®);
|
||||
reg &= ~LDO_VOL_MASK;
|
||||
reg |= (LDOB_3_30V | (1 << LDO_EN));
|
||||
pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#elif defined(CONFIG_DM_PMIC_PFUZE100)
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
|
|
@ -160,14 +353,176 @@ int power_init_board(void)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* set SW1AB staby volatage 0.975V*/
|
||||
reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
|
||||
reg &= ~0x3f;
|
||||
reg |= PFUZE100_SW1ABC_SETP(11000);
|
||||
pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
|
||||
|
||||
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||
reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
|
||||
|
||||
/* set SW1C staby volatage 0.975V*/
|
||||
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
|
||||
reg &= ~0x3f;
|
||||
reg |= PFUZE100_SW1ABC_SETP(11000);
|
||||
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
|
||||
|
||||
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
|
||||
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
|
||||
|
||||
/* Enable power of VGEN5 3V3, needed for SD3 */
|
||||
reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
|
||||
reg &= ~LDO_VOL_MASK;
|
||||
reg |= (LDOB_3_30V | (1 << LDO_EN));
|
||||
pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LDO_BYPASS_CHECK
|
||||
#ifdef CONFIG_POWER
|
||||
void ldo_mode_set(int ldo_bypass)
|
||||
{
|
||||
unsigned int value;
|
||||
int is_400M;
|
||||
u32 vddarm;
|
||||
struct pmic *p = pmic_get("PFUZE100");
|
||||
|
||||
if (!p) {
|
||||
printf("No PMIC found!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* switch to ldo_bypass mode */
|
||||
if (ldo_bypass) {
|
||||
prep_anatop_bypass();
|
||||
/* decrease VDDARM to 1.275V */
|
||||
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(12750);
|
||||
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
/* decrease VDDSOC to 1.3V */
|
||||
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(13000);
|
||||
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
||||
|
||||
is_400M = set_anatop_bypass(1);
|
||||
if (is_400M)
|
||||
vddarm = PFUZE100_SW1ABC_SETP(10750);
|
||||
else
|
||||
vddarm = PFUZE100_SW1ABC_SETP(11750);
|
||||
|
||||
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= vddarm;
|
||||
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
|
||||
|
||||
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(11750);
|
||||
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
|
||||
|
||||
finish_anatop_bypass();
|
||||
printf("switch to ldo_bypass mode!\n");
|
||||
}
|
||||
|
||||
}
|
||||
#elif defined(CONFIG_DM_PMIC_PFUZE100)
|
||||
void ldo_mode_set(int ldo_bypass)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
int is_400M;
|
||||
u32 vddarm;
|
||||
|
||||
ret = pmic_get("pfuze100", &dev);
|
||||
if (ret == -ENODEV) {
|
||||
printf("No PMIC found!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* switch to ldo_bypass mode , boot on 800Mhz */
|
||||
if (ldo_bypass) {
|
||||
prep_anatop_bypass();
|
||||
|
||||
/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
|
||||
pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
|
||||
|
||||
/* increase VDDSOC to 1.3V */
|
||||
pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
|
||||
|
||||
is_400M = set_anatop_bypass(1);
|
||||
if (is_400M)
|
||||
vddarm = PFUZE100_SW1ABC_SETP(10750);
|
||||
else
|
||||
vddarm = PFUZE100_SW1ABC_SETP(11750);
|
||||
|
||||
pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
|
||||
|
||||
/* decrease VDDSOC to 1.175V */
|
||||
pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
|
||||
|
||||
finish_anatop_bypass();
|
||||
printf("switch to ldo_bypass mode!\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#ifndef CONFIG_DM_USB
|
||||
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
|
||||
static iomux_v3_cfg_t const usb_otg_pads[] = {
|
||||
/* OGT1 */
|
||||
MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
/* OTG2 */
|
||||
MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
|
||||
};
|
||||
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
||||
ARRAY_SIZE(usb_otg_pads));
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
if (port == 1)
|
||||
return USB_INIT_HOST;
|
||||
else
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port > 1)
|
||||
return -EINVAL;
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
|
|
@ -188,8 +543,22 @@ int board_phy_config(struct phy_device *phydev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IMX_RDC
|
||||
static rdc_peri_cfg_t const shared_resources[] = {
|
||||
(RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)),
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_IMX_RDC
|
||||
imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_AUXCORE_FASTUP
|
||||
arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA);
|
||||
#endif
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
|
||||
|
|
@ -199,13 +568,112 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR},
|
||||
#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
|
||||
{USDHC4_BASE_ADDR, 0, 8},
|
||||
#else
|
||||
{USDHC4_BASE_ADDR},
|
||||
#endif
|
||||
};
|
||||
|
||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
|
||||
#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
|
||||
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
return devno - 1;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
return dev_no + 1;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = 1; /* Assume uSDHC2 is always present */
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
||||
break;
|
||||
case USDHC4_BASE_ADDR:
|
||||
#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
|
||||
ret = 1;
|
||||
#else
|
||||
ret = !gpio_get_value(USDHC4_CD_GPIO);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-Boot device node) (Physical Port)
|
||||
* mmc0 USDHC2
|
||||
* mmc1 USDHC3
|
||||
* mmc2 USDHC4
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
|
||||
gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr");
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
gpio_direction_output(USDHC3_PWR_GPIO, 1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
case 2:
|
||||
#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads));
|
||||
#else
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
gpio_request(USDHC4_CD_GPIO, "usdhc4 cd");
|
||||
gpio_direction_input(USDHC4_CD_GPIO);
|
||||
#endif
|
||||
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret) {
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
|
||||
#ifndef CONFIG_DM_SPI
|
||||
#define QSPI_PAD_CTRL1 \
|
||||
(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
|
||||
|
|
@ -226,13 +694,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = {
|
|||
MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_SPI
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads,
|
||||
ARRAY_SIZE(quadspi_pads));
|
||||
|
||||
#endif
|
||||
/* Set the clock */
|
||||
enable_qspi_clk(1);
|
||||
|
||||
|
|
@ -240,7 +710,25 @@ int board_qspi_init(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
|
||||
{"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
|
||||
{"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
|
||||
/* CABC enable */
|
||||
MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
/* Use GPIO for Brightness adjustment, duty cycle = period */
|
||||
MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
|
|
@ -276,9 +764,43 @@ static iomux_v3_cfg_t const lcd_pads[] = {
|
|||
MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static int setup_lcd(void)
|
||||
void do_enable_lvds(struct display_info_t const *dev)
|
||||
{
|
||||
enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
|
||||
int ret;
|
||||
|
||||
ret = enable_lcdif_clock(dev->bus, 1);
|
||||
if (ret) {
|
||||
printf("Enable LCDIF clock failed, %d\n", ret);
|
||||
return;
|
||||
}
|
||||
ret = enable_lvds_bridge(dev->bus);
|
||||
if (ret) {
|
||||
printf("Enable LVDS bridge failed, %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
|
||||
ARRAY_SIZE(lvds_ctrl_pads));
|
||||
|
||||
/* Enable CABC */
|
||||
gpio_request(IMX_GPIO_NR(4, 18), "CABC enable");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 18) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
gpio_request(IMX_GPIO_NR(6, 3), "lvds backlight");
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
|
||||
}
|
||||
|
||||
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
||||
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = enable_lcdif_clock(dev->bus, 1);
|
||||
if (ret) {
|
||||
printf("Enable LCDIF clock failed, %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
|
|
@ -291,9 +813,48 @@ static int setup_lcd(void)
|
|||
/* Set Brightness to high */
|
||||
gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = LCDIF2_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 18,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_lvds,
|
||||
.mode = {
|
||||
.name = "Hannstar-XGA",
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = MX6SX_LCDIF1_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 24,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "MCIMX28LCD",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
|
|
@ -314,12 +875,28 @@ int board_init(void)
|
|||
gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#ifndef CONFIG_DM_USB
|
||||
setup_usb();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
setup_lcd();
|
||||
#ifdef CONFIG_PCIE_IMX
|
||||
setup_pcie();
|
||||
#endif
|
||||
|
||||
/* Also used for OF_CONTROL enabled */
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec(CONFIG_FEC_ENET_DEV);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
@ -336,6 +913,14 @@ int board_late_init(void)
|
|||
if (is_reva())
|
||||
env_set("board_rev", "REVA");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx6sx_sabresd_ddr_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x000c0000
|
||||
str r1, [r0, #0x618]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x5fc]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x32c]
|
||||
|
||||
ldr r1, =0x00000020
|
||||
str r1, [r0, #0x300]
|
||||
str r1, [r0, #0x2fc]
|
||||
str r1, [r0, #0x5f4]
|
||||
str r1, [r0, #0x340]
|
||||
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x320]
|
||||
ldr r1, =0x00000020
|
||||
str r1, [r0, #0x310]
|
||||
str r1, [r0, #0x314]
|
||||
str r1, [r0, #0x614]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x5f8]
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x330]
|
||||
str r1, [r0, #0x334]
|
||||
str r1, [r0, #0x338]
|
||||
str r1, [r0, #0x33c]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x608]
|
||||
ldr r1, =0x00000028
|
||||
str r1, [r0, #0x60c]
|
||||
str r1, [r0, #0x610]
|
||||
str r1, [r0, #0x61c]
|
||||
str r1, [r0, #0x620]
|
||||
str r1, [r0, #0x2ec]
|
||||
str r1, [r0, #0x2f0]
|
||||
str r1, [r0, #0x2f4]
|
||||
str r1, [r0, #0x2f8]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r2, =0xa1390003
|
||||
str r2, [r0, #0x800]
|
||||
ldr r2, =0x00290025
|
||||
str r2, [r0, #0x80c]
|
||||
ldr r2, =0x00220022
|
||||
str r2, [r0, #0x810]
|
||||
ldr r2, =0x41480144
|
||||
str r2, [r0, #0x83c]
|
||||
ldr r2, =0x01340130
|
||||
str r2, [r0, #0x840]
|
||||
ldr r2, =0x3C3E4244
|
||||
str r2, [r0, #0x848]
|
||||
ldr r2, =0x34363638
|
||||
str r2, [r0, #0x850]
|
||||
|
||||
ldr r2, =0x33333333
|
||||
str r2, [r0, #0x81c]
|
||||
str r2, [r0, #0x820]
|
||||
str r2, [r0, #0x824]
|
||||
str r2, [r0, #0x828]
|
||||
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x8b8]
|
||||
ldr r2, =0x0002002d
|
||||
str r2, [r0, #0x004]
|
||||
ldr r2, =0x00333030
|
||||
str r2, [r0, #0x008]
|
||||
ldr r2, =0x676b52f3
|
||||
str r2, [r0, #0x00c]
|
||||
ldr r2, =0xb66d8b63
|
||||
str r2, [r0, #0x010]
|
||||
ldr r2, =0x01ff00db
|
||||
str r2, [r0, #0x014]
|
||||
ldr r2, =0x00011740
|
||||
str r2, [r0, #0x018]
|
||||
ldr r2, =0x00008000
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x000026d2
|
||||
str r2, [r0, #0x02c]
|
||||
ldr r2, =0x006b1023
|
||||
str r2, [r0, #0x030]
|
||||
ldr r2, =0x0000005f
|
||||
str r2, [r0, #0x040]
|
||||
ldr r2, =0x84190000
|
||||
str r2, [r0, #0x000]
|
||||
ldr r2, =0x04008032
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00008033
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00048031
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x05208030
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x04008040
|
||||
str r2, [r0, #0x01c]
|
||||
ldr r2, =0x00000800
|
||||
str r2, [r0, #0x020]
|
||||
ldr r2, =0x00011117
|
||||
str r2, [r0, #0x818]
|
||||
ldr r2, =0x00000000
|
||||
str r2, [r0, #0x01c]
|
||||
.endm
|
||||
.macro imx6_clock_gating
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0xffffffff
|
||||
str r1, [r0, #0x068]
|
||||
str r1, [r0, #0x06c]
|
||||
str r1, [r0, #0x070]
|
||||
str r1, [r0, #0x074]
|
||||
str r1, [r0, #0x078]
|
||||
str r1, [r0, #0x07c]
|
||||
str r1, [r0, #0x080]
|
||||
str r1, [r0, #0x084]
|
||||
.endm
|
||||
|
||||
.macro imx6_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx6_ddr_setting
|
||||
imx6sx_sabresd_ddr_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx6_plugin.S>
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6SX Sabresd board.
|
||||
*
|
||||
|
|
@ -18,20 +19,32 @@
|
|||
#endif
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
#ifdef CONFIG_IMX_BOOTAUX
|
||||
/* Set to QSPI2 B flash at default */
|
||||
#ifdef CONFIG_DM_SPI
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
|
||||
#define SF_QSPI2_B_CS_NUM 2
|
||||
#elif defined(CONFIG_MX6SX_SABRESD_REVA)
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x71000000
|
||||
#define SF_QSPI2_B_CS_NUM 1
|
||||
#else
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000
|
||||
#define SF_QSPI2_B_CS_NUM 1
|
||||
#endif
|
||||
|
||||
/* When using M4 fastup demo, no need these M4 env, since QSPI is used by M4 */
|
||||
#ifndef CONFIG_SYS_AUXCORE_FASTUP
|
||||
#define UPDATE_M4_ENV \
|
||||
"m4image=m4_qspi.bin\0" \
|
||||
"m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \
|
||||
"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
|
||||
"update_m4_from_sd=" \
|
||||
"if sf probe 1:0; then " \
|
||||
"if sf probe 1:${m4_qspi_cs}; then " \
|
||||
"if run loadm4image; then " \
|
||||
"setexpr fw_sz ${filesize} + 0xffff; " \
|
||||
"setexpr fw_sz ${fw_sz} / 0x10000; " \
|
||||
|
|
@ -40,13 +53,31 @@
|
|||
"sf write ${loadaddr} 0x0 ${filesize}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
|
||||
"m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
|
||||
#else
|
||||
#define UPDATE_M4_ENV ""
|
||||
#endif
|
||||
#endif /* CONFIG_SYS_AUXCORE_FASTUP */
|
||||
|
||||
#else
|
||||
#define UPDATE_M4_ENV ""
|
||||
#endif /* CONFIG_IMX_BOOTAUX */
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
UPDATE_M4_ENV \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
|
|
@ -54,15 +85,16 @@
|
|||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx6sx-sdb.dtb\0" \
|
||||
"fdt_addr=0x88000000\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
|
||||
"mmcdev=2\0" \
|
||||
"panel=Hannstar-XGA\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=1\0" \
|
||||
"finduuid=part uuid mmc 2:2 uuid\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=PARTUUID=${uuid} rootwait rw\0" \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
|
|
@ -70,7 +102,6 @@
|
|||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run finduuid; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
|
|
@ -144,26 +175,57 @@
|
|||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* MMC Configuration */
|
||||
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
|
||||
|
||||
/* I2C Configs */
|
||||
#ifndef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#endif
|
||||
|
||||
/* PMIC */
|
||||
#ifndef CONFIG_DM_PMIC
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE100
|
||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
||||
#endif
|
||||
|
||||
/* Network */
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
|
||||
#define CONFIG_FEC_ENET_DEV 1
|
||||
|
||||
#if (CONFIG_FEC_ENET_DEV == 0)
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
#ifdef CONFIG_DM_ETH
|
||||
#define CONFIG_ETHPRIME "eth0"
|
||||
#else
|
||||
#define CONFIG_ETHPRIME "FEC0"
|
||||
#endif
|
||||
#elif (CONFIG_FEC_ENET_DEV == 1)
|
||||
#define IMX_FEC_BASE ENET2_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x2
|
||||
#ifdef CONFIG_DM_ETH
|
||||
#define CONFIG_ETHPRIME "eth1"
|
||||
#else
|
||||
#define CONFIG_ETHPRIME "FEC1"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE ENET_BASE_ADDR
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
|
|
@ -182,7 +244,6 @@
|
|||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_SYS_FSL_QSPI_LE
|
||||
#define CONFIG_SYS_FSL_QSPI_AHB
|
||||
#ifdef CONFIG_MX6SX_SABRESD_REVA
|
||||
#define FSL_QSPI_FLASH_SIZE SZ_16M
|
||||
|
|
@ -190,6 +251,10 @@
|
|||
#define FSL_QSPI_FLASH_SIZE SZ_32M
|
||||
#endif
|
||||
#define FSL_QSPI_FLASH_NUM 2
|
||||
#define CONFIG_SF_DEFAULT_BUS 1
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
|
@ -201,16 +266,29 @@
|
|||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#define CONFIG_SYS_CONSOLE_BG_COL 0x00
|
||||
#define CONFIG_SYS_CONSOLE_FG_COL 0xa0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (896 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* USDHC4 */
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -2144,6 +2144,7 @@ CONFIG_SYS_ATMEL_TOTALSECT
|
|||
CONFIG_SYS_AUTOLOAD
|
||||
CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
|
||||
CONFIG_SYS_AUXCORE_BOOTDATA
|
||||
CONFIG_SYS_AUXCORE_FASTUP
|
||||
CONFIG_SYS_BARGSIZE
|
||||
CONFIG_SYS_BAUDRATE_TABLE
|
||||
CONFIG_SYS_BCSR
|
||||
|
|
|
|||
Loading…
Reference in New Issue