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ppc4xx: DDR2: Complete RDSS configuration on non-SPD based boards 

As described in item #10 of the SDRAM initialization (chapter 22.2.9
of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The
code for this is now factored out and executed for non-SPD based boards
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2010-05-25 15:33:14 +02:00
parent 066003b2c5
commit e9c020df96
1 changed files with 38 additions and 14 deletions
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52
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -68,6 +68,31 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void update_rdcc(void)
{
u32 val;
/*
* Complete RDSS configuration as mentioned on page 7 of the AMCC
* PowerPC440SP/SPe DDR2 application note:
* "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
*
* Or item #10 "10. Complete RDSS configuration" in chapter
* "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
* manual.
*/
mfsdram(SDRAM_RTSR, val);
if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
mfsdram(SDRAM_RDCC, val);
if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
val += 0x40000000;
mtsdram(SDRAM_RDCC, val);
}
}
}
#endif
#if defined(CONFIG_440)
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2
@ -620,6 +645,12 @@ phys_size_t initdram(int board_type)
#else
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
#endif
/*
* Now complete RDSS configuration as mentioned on page 7 of the AMCC
* PowerPC440SP/SPe DDR2 application note:
* "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
*/
update_rdcc();
#ifdef CONFIG_DDR_ECC
/*------------------------------------------------------------------
@ -2692,20 +2723,6 @@ calibration_loop:
blank_string(strlen(str));
#endif /* CONFIG_DDR_RQDC_FIXED */
/*
* Now complete RDSS configuration as mentioned on page 7 of the AMCC
* PowerPC440SP/SPe DDR2 application note:
* "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
*/
mfsdram(SDRAM_RTSR, val);
if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
mfsdram(SDRAM_RDCC, val);
if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
val += 0x40000000;
mtsdram(SDRAM_RDCC, val);
}
}
mfsdram(SDRAM_DLCR, val);
debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
mfsdram(SDRAM_RQDC, val);
@ -3007,6 +3024,13 @@ phys_size_t initdram(int board_type)
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
* Now complete RDSS configuration as mentioned on page 7 of the AMCC
* PowerPC440SP/SPe DDR2 application note:
* "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
*/
update_rdcc();
#if defined(CONFIG_DDR_ECC)
do_program_ecc(0);
#endif /* defined(CONFIG_DDR_ECC) */