LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

clk: imx8m: drop clk settings 

We use non-dm code to configure the clk settings in order to simplify
dm clk driver in future, so remove the duplicated code from clk driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2020-07-09 15:36:22 +08:00
parent 6036dba1c8
commit ec04ae4217
2 changed files with 0 additions and 68 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/clk/imx/clk-imx8mm.c
View File

@ -437,40 +437,6 @@ static int imx8mm_clk_probe(struct udevice *dev)
base + 0x40a0, 0)); base + 0x40a0, 0));
#endif #endif
#ifdef CONFIG_SPL_BUILD
struct clk *clkp, *clkp1;
clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp);
clk_enable(clkp);
clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp);
clk_enable(clkp);
clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp);
clk_enable(clkp);
/* Configure SYS_PLL3 to 750MHz */
clk_get_by_id(IMX8MM_SYS_PLL3, &clkp);
clk_set_rate(clkp, 750000000UL);
clk_enable(clkp);
/* Configure ARM to sys_pll2_500m */
clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
clk_get_by_id(IMX8MM_SYS_PLL2_OUT, &clkp1);
clk_enable(clkp1);
clk_get_by_id(IMX8MM_SYS_PLL2_500M, &clkp1);
clk_set_parent(clkp, clkp1);
/* Configure ARM PLL to 1.2GHz */
clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
clk_set_rate(clkp1, 1200000000UL);
clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
clk_enable(clkp1);
clk_set_parent(clkp, clkp1);
/* Configure DIV to 1.2GHz */
clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
clk_set_rate(clkp1, 1200000000UL);
#endif
return 0; return 0;
} }

34
drivers/clk/imx/clk-imx8mn.c
View File

@ -440,40 +440,6 @@ static int imx8mn_clk_probe(struct udevice *dev)
base + 0x40a0, 0)); base + 0x40a0, 0));
#endif #endif
#ifdef CONFIG_SPL_BUILD
struct clk *clkp, *clkp1;
clk_get_by_id(IMX8MN_CLK_WDOG1_ROOT, &clkp);
clk_enable(clkp);
clk_get_by_id(IMX8MN_CLK_WDOG2_ROOT, &clkp);
clk_enable(clkp);
clk_get_by_id(IMX8MN_CLK_WDOG3_ROOT, &clkp);
clk_enable(clkp);
/* Configure SYS_PLL3 to 600MHz */
clk_get_by_id(IMX8MN_SYS_PLL3, &clkp);
clk_set_rate(clkp, 600000000UL);
clk_enable(clkp);
/* Configure ARM to sys_pll2_500m */
clk_get_by_id(IMX8MN_CLK_A53_SRC, &clkp);
clk_get_by_id(IMX8MN_SYS_PLL2_OUT, &clkp1);
clk_enable(clkp1);
clk_get_by_id(IMX8MN_SYS_PLL2_500M, &clkp1);
clk_set_parent(clkp, clkp1);
/* Configure ARM PLL to 1.2GHz */
clk_get_by_id(IMX8MN_ARM_PLL, &clkp1);
clk_set_rate(clkp1, 1200000000UL);
clk_get_by_id(IMX8MN_ARM_PLL_OUT, &clkp1);
clk_enable(clkp1);
clk_set_parent(clkp, clkp1);
/* Configure DIV to 1.2GHz */
clk_get_by_id(IMX8MN_CLK_A53_DIV, &clkp1);
clk_set_rate(clkp1, 1200000000UL);
#endif
return 0; return 0;
} }