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nbhw18: fpga pin mapping fix

This commit is contained in:
user 2018-02-22 08:44:00 +01:00
parent 44e0aea765
commit eedaeaa440
3 changed files with 3 additions and 4 deletions
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1
arch/arm/dts/armada-385-nbhw18-common.dtsi
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@ -47,6 +47,7 @@
spi-sdo = <&gpio1 6 0>; /* SDO slave data out */
spi-sck = <&gpio1 7 0>; /* SCK */
spi-sdi = <&gpio1 8 0>; /* SDI slave data in */
fpga-reset = <&gpio0 19 0>; /* FPGA reset */
fpga-reset-logic = <&gpio1 12 0>; /* FPGA reset logic (after load)*/
};

3
arch/arm/dts/armada-385-nbhw18-v1.dts
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@ -18,8 +18,7 @@
soc {
gpiofpga: gpio@fd0000000 {
fpga-reset = <&gpio0 19 0>; /* FPGA reset */
fpga-cdone = <&gpio0 29 0>; /* FPGA cdone */
fpga-cdone = <&gpio0 29 0>; /* FPGA cdone HW V1 */
};
};
};

3
arch/arm/dts/armada-385-nbhw18-v2.dts
View File

@ -18,8 +18,7 @@
soc {
gpiofpga: gpio@fd0000000 {
fpga-reset = <&gpio0 19 0>; /* FPGA reset */
fpga-cdone = <&gpio0 21 0>; /* FPGA cdone */
fpga-cdone = <&gpio0 29 0>; /* FPGA cdone HW V1 (TODO: For V2 use 21 instead of 29. Cannot change it while still using old hw due to conflict with eth phy reset. ) */
};
};
};