PPC4xx: Use common code for LWMON5 board SDRAM support
This patch also modifies the functionality of the code so that the data-eye search is now done with with the cache disabled. Signed-off-by: Larry Johnson <lrj@acm.org>
This commit is contained in:
Larry Johnson
Stefan Roese
parent
62cc3951ab
commit
ef16fccf96
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@ -36,8 +36,6 @@
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#include <asm/io.h>
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#include <ppc440.h>
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#include "sdram.h"
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/*
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* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
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* region. Right now the cache should still be disabled in U-Boot because of the
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@ -54,8 +52,13 @@
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
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#endif
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void dcbz_area(u32 start_address, u32 num_bytes);
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void dflush(void);
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/*-----------------------------------------------------------------------------+
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* Prototypes
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*-----------------------------------------------------------------------------*/
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extern int denali_wait_for_dlllock(void);
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extern void denali_core_search_data_eye(void);
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extern void dcbz_area(u32 start_address, u32 num_bytes);
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extern void dflush(void);
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static u32 is_ecc_enabled(void)
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{
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@ -87,330 +90,6 @@ void board_add_ram_info(int use_default)
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printf(", CL%d)", val);
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}
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static int wait_for_dlllock(void)
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{
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u32 val;
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int wait = 0;
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/*
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* Wait for the DCC master delay line to finish calibration
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*/
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mtdcr(ddrcfga, DDR0_17);
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val = DDR0_17_DLLLOCKREG_UNLOCKED;
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
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/* dlllockreg bit on */
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return 0;
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else
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wait++;
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}
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debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
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debug("Waiting for dlllockreg bit to raise\n");
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return -1;
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}
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#if defined(CONFIG_DDR_DATA_EYE)
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int wait_for_dram_init_complete(void)
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{
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u32 val;
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int wait = 0;
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/*
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* Wait for 'DRAM initialization complete' bit in status register
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*/
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mtdcr(ddrcfga, DDR0_00);
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
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/* 'DRAM initialization complete' bit */
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return 0;
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else
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wait++;
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}
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debug("DRAM initialization complete bit in status register did not rise\n");
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return -1;
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}
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#define NUM_TRIES 64
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#define NUM_READS 10
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void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
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{
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int k, j;
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u32 val;
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u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
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u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
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u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
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u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
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volatile u32 *ram_pointer;
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u32 test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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ram_pointer = (volatile u32 *)start_addr;
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for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
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/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
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/*
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* De-assert 'start' parameter.
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*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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/*
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* Set 'wr_dqs_shift'
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*/
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mtdcr(ddrcfga, DDR0_09);
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val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
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| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
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mtdcr(ddrcfgd, val);
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/*
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* Set 'dqs_out_shift' = wr_dqs_shift + 32
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*/
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dqs_out_shift = wr_dqs_shift + 32;
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mtdcr(ddrcfga, DDR0_22);
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val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
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| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
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mtdcr(ddrcfgd, val);
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passing_cases = 0;
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for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
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/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
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/*
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* Set 'dll_dqs_delay_X'.
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*/
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/* dll_dqs_delay_0 */
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mtdcr(ddrcfga, DDR0_17);
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val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
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| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_1 to dll_dqs_delay_4 */
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mtdcr(ddrcfga, DDR0_18);
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val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
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| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_5 to dll_dqs_delay_8 */
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mtdcr(ddrcfga, DDR0_19);
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val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
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| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/*
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* Assert 'start' parameter.
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*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/*
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* Wait for the DCC master delay line to finish calibration
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*/
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if (wait_for_dlllock() != 0) {
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printf("dlllock did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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ppcMsync();
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ppcMbar();
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if (wait_for_dram_init_complete() != 0) {
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printf("dram init complete did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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udelay(100); /* wait 100us to ensure init is really completed !!! */
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS)
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break;
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}
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/* See if the dll_dqs_delay_X value passed.*/
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if (j < NUM_TRIES) {
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/* Failed */
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passing_cases = 0;
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/* break; */
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} else {
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/* Passed */
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if (passing_cases == 0)
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dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
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passing_cases++;
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if (passing_cases >= max_passing_cases) {
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max_passing_cases = passing_cases;
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wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
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dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
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dll_dqs_delay_X_end_window = dll_dqs_delay_X;
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}
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}
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/*
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* De-assert 'start' parameter.
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*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
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} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
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/*
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* Largest passing window is now detected.
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*/
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/* Compute dll_dqs_delay_X value */
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dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
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wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
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debug("DQS calibration - Window detected:\n");
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debug("max_passing_cases = %d\n", max_passing_cases);
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debug("wr_dqs_shift = %d\n", wr_dqs_shift);
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debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
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debug("dll_dqs_delay_X window = %d - %d\n",
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dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
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/*
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* De-assert 'start' parameter.
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*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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/*
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* Set 'wr_dqs_shift'
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*/
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mtdcr(ddrcfga, DDR0_09);
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val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
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| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
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mtdcr(ddrcfgd, val);
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debug("DDR0_09=0x%08lx\n", val);
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/*
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* Set 'dqs_out_shift' = wr_dqs_shift + 32
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*/
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dqs_out_shift = wr_dqs_shift + 32;
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mtdcr(ddrcfga, DDR0_22);
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val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
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| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
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mtdcr(ddrcfgd, val);
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debug("DDR0_22=0x%08lx\n", val);
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/*
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* Set 'dll_dqs_delay_X'.
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*/
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/* dll_dqs_delay_0 */
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mtdcr(ddrcfga, DDR0_17);
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val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
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| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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debug("DDR0_17=0x%08lx\n", val);
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/* dll_dqs_delay_1 to dll_dqs_delay_4 */
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mtdcr(ddrcfga, DDR0_18);
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val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
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| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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debug("DDR0_18=0x%08lx\n", val);
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/* dll_dqs_delay_5 to dll_dqs_delay_8 */
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mtdcr(ddrcfga, DDR0_19);
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val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
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| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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debug("DDR0_19=0x%08lx\n", val);
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/*
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* Assert 'start' parameter.
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*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/*
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* Wait for the DCC master delay line to finish calibration
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*/
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if (wait_for_dlllock() != 0) {
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printf("dlllock did not occur !!!\n");
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hang();
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}
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ppcMsync();
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ppcMbar();
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if (wait_for_dram_init_complete() != 0) {
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printf("dram init complete did not occur !!!\n");
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hang();
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}
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udelay(100); /* wait 100us to ensure init is really completed !!! */
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}
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#endif /* CONFIG_DDR_DATA_EYE */
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#ifdef CONFIG_DDR_ECC
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static void wait_ddr_idle(void)
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{
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@ -610,12 +289,23 @@ long int initdram (int board_type)
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mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
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#endif
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wait_for_dlllock();
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denali_wait_for_dlllock();
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#if defined(CONFIG_DDR_DATA_EYE)
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/* -----------------------------------------------------------+
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* Perform data eye search if requested.
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* ----------------------------------------------------------*/
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program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
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TLB_WORD2_I_ENABLE);
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denali_core_search_data_eye();
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remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
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#endif
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/*
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* Program tlb entries for this size (dynamic)
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*/
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program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
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program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
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MY_TLB_WORD2_I_ENABLE);
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/*
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* Setup 2nd TLB with same physical address but different virtual address
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@ -623,13 +313,6 @@ long int initdram (int board_type)
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*/
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program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
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#ifdef CONFIG_DDR_DATA_EYE
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/*
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* Perform data eye search if requested.
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*/
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denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
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#endif
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#ifdef CONFIG_DDR_ECC
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/*
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* If ECC is enabled, initialize the parity bits.
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