diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bfb31e8dd..83e34c7862 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -988,7 +988,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ k3-am642-r5-evm.dtb \ k3-am642-sk.dtb \ k3-am642-r5-sk.dtb \ - k3-am642-evm-nand.dtbo + k3-am642-evm-nand.dtbo \ + k3-am642-gemini-v1.dtb \ + k3-am642-r5-gemini-v1.dtb dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-r5-sk.dtb diff --git a/arch/arm/dts/k3-am642-gemini-v1.dts b/arch/arm/dts/k3-am642-gemini-v1.dts new file mode 100644 index 0000000000..b7d4d6a185 --- /dev/null +++ b/arch/arm/dts/k3-am642-gemini-v1.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am642.dtsi" + +/ { + compatible = "ti,am642-gemini", "ti,am642"; + model = "NetModule AM642 based Gemini"; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 1G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; + +&main_pmx0 { + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ + AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ + >; + }; + + gpio0_pins: gpio0-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPIO0_35 */ + AM64X_IOPAD(0x008C, PIN_INPUT, 7) /* (T21) GPIO0_34 */ + AM64X_IOPAD(0x00A0, PIN_INPUT, 7) /* (N16) GPIO0_39 */ + AM64X_IOPAD(0x0098, PIN_INPUT, 7) /* (W19) GPIO0_37 */ + AM64X_IOPAD(0x009C, PIN_INPUT, 7) /* (Y18) GPIO0_38 */ + AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (Y19) GPIO0_36 */ + AM64X_IOPAD(0x00A8, PIN_INPUT, 7) /* (R19) GPIO0_41 */ + AM64X_IOPAD(0x00AC, PIN_INPUT, 7) /* (R20) GPIO0_42 */ + AM64X_IOPAD(0x00A4, PIN_INPUT, 7) /* (N17) GPIO0_40 */ + + AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* (AA13) GPIO0_70 */ + AM64X_IOPAD(0x0128, PIN_OUTPUT, 7) /* (U12) GPIO0_73 */ + AM64X_IOPAD(0x0150, PIN_INPUT, 7) /* (Y13) GPIO0_20 */ + AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) GPIO0_84 */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* (W13) GPIO0_53 */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* (V13) GPIO0_50 */ + + AM64X_IOPAD(0x0124, PIN_OUTPUT, 7) /* (V15) GPIO0_72 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 7) /* (V14) GPIO0_74 */ + AM64X_IOPAD(0x0130, PIN_INPUT, 7) /* (W14) GPIO0_75 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 7) /* (AA14) GPIO0_19 */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 7) /* (U14) GPIO0_55 */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (U15) GPIO0_54 */ + + AM64X_IOPAD(0x0114, PIN_INPUT, 7) /* (Y12) GPIO0_68 */ + AM64X_IOPAD(0x0118, PIN_OUTPUT, 7) /* (W12) GPIO0_69 */ + + + AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ + AM64X_IOPAD(0x00c0, PIN_OUTPUT, 7) /* (W8) GPIO0_47 */ + AM64X_IOPAD(0x00c4, PIN_OUTPUT, 7) /* (W8) GPIO0_48 */ + AM64X_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (W8) GPIO0_49 */ + AM64X_IOPAD(0x00fc, PIN_INPUT, 7) /* (U7) GPIO0_62 */ + + AM64X_IOPAD(0x002c, PIN_OUTPUT, 7) /* (L19) GPIO0_11 */ + AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) GPIO0_12 */ + AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* (K17) GPIO0_13 */ + AM64X_IOPAD(0x0038, PIN_OUTPUT, 7) /* (L17) GPIO0_14 */ + + AM64X_IOPAD(0x0014, PIN_OUTPUT, 7) /* (M20) GPIO0_5 */ + AM64X_IOPAD(0x0018, PIN_OUTPUT, 7) /* (M21) GPIO0_6 */ + AM64X_IOPAD(0x001c, PIN_OUTPUT, 7) /* (P21) GPIO0_7 */ + AM64X_IOPAD(0x0020, PIN_OUTPUT, 7) /* (P20) GPIO0_8 */ + AM64X_IOPAD(0x0024, PIN_OUTPUT, 7) /* (N18) GPIO0_9 */ + AM64X_IOPAD(0x0028, PIN_OUTPUT, 7) /* (M17) GPIO0_10 */ + + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT, 1) /* (P19) I2C2_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT, 1) /* (R21) I2C2_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00B0, PIN_INPUT, 1) /* (P19) I2C2_SCL */ + AM64X_IOPAD(0x00B4, PIN_INPUT, 1) /* (R21) I2C2_SDA */ + >; + }; + + rmii1_pins_default: rmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01cc, PIN_INPUT, 5) /* (W5) PRG0_PRU1_GPO7.RMII1_RD0 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 5) /* (Y5) PRG0_PRU1_GPO9.RMII1_RD1 */ + AM64X_IOPAD(0x01d8, PIN_OUTPUT, 5) /* (V6) PRG0_PRU1_GPO10.RMII1_TD0 */ + AM64X_IOPAD(0x01f4, PIN_OUTPUT, 5) /* (V5) PRG0_PRU1_GPO17.RMII1_TD1 */ + AM64X_IOPAD(0x01fc, PIN_INPUT, 5) /* (R2) PRG0_PRU1_GPO17.RMII1_CRS_DV*/ + AM64X_IOPAD(0x01f8, PIN_INPUT, 5) /* (P5) PRG0_PRU1_GPO17.RMII1_TX_EN */ + AM64X_IOPAD(0x0188, PIN_INPUT, 5) /* (AA5) PRG0_PRU0_GPO10.RMII1_REF_CLK*/ + >; + }; + + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 4) /* (Y6) PRG1_MDIO0_MDC.MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 4) /* (AA6) PRG1_MDIO0_MDIO.MDIO0_MDIO */ + + AM64X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (W1) GPIO1_19 */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ + AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ + >; + }; +}; + +/* SYS_I2C */ +&main_i2c1 { + status = "disabled"; + + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + /* There is no driver available */ + onewire: ds2484@18 { + status = "disabled"; + reg = <0x18>; + }; + + eeprom: eeprom@50 { + reg = <0x50>; + compatible = "onsemi,24c64"; + }; + + temp: temp@48 { + reg = <0x48>; + compatible = "national,lm75"; + /* vs-supply = <&vs>; */ /* Not available, maybe required then use fixed-regulator */ + }; +}; + +/* USER_I2C */ +&main_i2c2 { + status = "disabled"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <100000>; + + exp1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPI_CTRL_PU_EN0", "GPI_CTRL_PU_EN1", + "GPI_CTRL_PU_EN2", "GPI_CTRL_PU_EN3", + "GPI_CTRL_PU_EN4", "GPI_CTRL_PU_EN5", + "", ""; + }; + + exp2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO0", "GPIO1", + "GPIO2", "GPIO3", + "GPO0", "GPO1", + "GPO2", "GPO3"; + }; + +}; + +&sdhci0 { + /* emmc */ + bus-width = <8>; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&sdhci1 { + /delete-property/ pinctrl-0; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default + &rmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rmii"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; diff --git a/arch/arm/dts/k3-am642-r5-gemini-v1.dts b/arch/arm/dts/k3-am642-r5-gemini-v1.dts new file mode 100644 index 0000000000..e2101578b4 --- /dev/null +++ b/arch/arm/dts/k3-am642-r5-gemini-v1.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am642.dtsi" +#include "k3-am64-evm-ddr4-1600MTs.dtsi" +#include "k3-am64-ddr.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + memory@80000000 { + device_type = "memory"; + /* 1G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + + u-boot,dm-spl; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1000000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + u-boot,dm-spl; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + clk_200mhz: dummy-clock-200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + u-boot,dm-spl; + }; + + vtt_supply: vtt-supply { + compatible = "regulator-gpio"; + regulator-name = "vtt"; + regulator-min-microvolt = <0>; + regulator-max-microvolt = <3300000>; + gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; + states = <0 0x0 3300000 0x1>; + u-boot,dm-spl; + }; +}; + +&cbass_main { + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; + mbox-names = "tx", "rx"; + u-boot,dm-spl; + }; +}; + +&cbass_main { + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x420000 0x0 0x1000>; + ti,esm-pins = <160>, <161>; + u-boot,dm-spl; + }; +}; + +&cbass_mcu { + u-boot,dm-spl; + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x4100000 0x0 0x1000>; + ti,esm-pins = <0>, <1>; + u-boot,dm-spl; + }; +}; + +&main_pmx0 { + u-boot,dm-spl; + main_uart0_pins_default: main-uart0-pins-default { + u-boot,dm-spl; + pinctrl-single,pins = < + AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ + AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ + AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + u-boot,dm-spl; + pinctrl-single,pins = < + AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ + >; + }; + + main_mmc1_pins_default: main-mmc0-pins-default { + }; + + ddr_vtt_pins_default: ddr-vtt-pins-default { + u-boot,dm-spl; + pinctrl-single,pins = < + AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ + >; + }; + + main_usb0_pins_default: main-usb0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ + AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ + >; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&main_uart0 { + /delete-property/ power-domains; + /delete-property/ clocks; + /delete-property/ clock-names; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&memorycontroller { + vtt-supply = <&vtt_supply>; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; +}; + +&sdhci0 { + /delete-property/ power-domains; + clocks = <&clk_200mhz>; + clock-names = "clk_xin"; + ti,driver-strength-ohm = <50>; + disable-wp; + pinctrl-0 = <&main_mmc0_pins_default>; +}; + +&sdhci1 { + /delete-property/ pinctrl-0; +}; + +&main_gpio0 { + u-boot,dm-spl; + /delete-property/ power-domains; +}; + +&usbss0 { + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins_default>; +}; + +/* EEPROM might be read before SYSFW is available */ +&main_i2c0 { + /delete-property/ power-domains; +}; + +&main_gpio0 { + u-boot,dm-spl; +}; + +#include "k3-am642-evm-u-boot.dtsi" diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 5eca68e78d..74835283cf 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -192,4 +192,6 @@ source "board/ti/am64x/Kconfig" source "board/ti/am62x/Kconfig" source "board/ti/j721e/Kconfig" source "board/ti/j721s2/Kconfig" + +source "board/nm/am64x/Kconfig" endif diff --git a/board/nm/am64x/Kconfig b/board/nm/am64x/Kconfig new file mode 100644 index 0000000000..4402ce9eac --- /dev/null +++ b/board/nm/am64x/Kconfig @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + +choice + prompt "NetModule boards" + optional + +config TARGET_AM642_A53_GEMINI + bool "TI K3 based AM642 Gemini Board from NetModule for A53" + select ARM64 + select SOC_K3_AM642 + imply BOARD + imply SPL_BOARD + +config TARGET_AM642_R5_GEMINI + bool "TI K3 based AM642 Gemini Board from NetModule for R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select SOC_K3_AM642 + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF +endchoice + +if TARGET_AM642_A53_GEMINI + +config SYS_BOARD + default "am64x" + +config SYS_VENDOR + default "nm" + +config SYS_CONFIG_NAME + default "am64x_gemini" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM642_R5_GEMINI + +config SYS_BOARD + default "am64x" + +config SYS_VENDOR + default "nm" + +config SYS_CONFIG_NAME + default "am64x_gemini" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +source "board/ti/common/Kconfig" + +endif diff --git a/board/nm/am64x/Makefile b/board/nm/am64x/Makefile new file mode 100644 index 0000000000..cc65a73b7d --- /dev/null +++ b/board/nm/am64x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ +# Keerthy +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += gemini.o diff --git a/board/nm/am64x/gemini.c b/board/nm/am64x/gemini.c new file mode 100644 index 0000000000..f076b9fb0e --- /dev/null +++ b/board/nm/am64x/gemini.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for AM642 EVM + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + * Keerthy + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + s32 ret; + + ret = fdtdec_setup_mem_size_base(); + if (ret) + printf("Error setting up mem size and base. %d\n", ret); + + return ret; +} + +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + return ret; +} +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(USB_STORAGE) +static int fixup_usb_boot(const void *fdt_blob) +{ + int ret = 0; + + switch (spl_boot_device()) { + case BOOT_DEVICE_USB: + /* + * If the boot mode is host, fixup the dr_mode to host + * before cdns3 bind takes place + */ + ret = fdt_find_and_setprop((void *)fdt_blob, + "/bus@f4000/cdns-usb@f900000/usb@f400000", + "dr_mode", "host", 5, 0); + if (ret) + printf("%s: fdt_find_and_setprop() failed:%d\n", + __func__, ret); + fallthrough; + default: + break; + } + + return ret; +} +#endif + +#if defined(CONFIG_K3_AM64_DDRSS) +static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); +} +#else +static void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} +#endif + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ +#if defined(CONFIG_K3_AM64_DDRSS) + fixup_ddr_driver_for_ecc(spl_image); +#else + fixup_memory_node(spl_image); +#endif + +#if CONFIG_IS_ENABLED(USB_STORAGE) + fixup_usb_boot(spl_image->fdt_addr); +#endif +} +#endif + +int checkboard(void) +{ + printf("Board: GEMINI rev 1\n"); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif + +#define CTRLMMR_USB0_PHY_CTRL 0x43004008 +#define CORE_VOLTAGE 0x80000000 + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + u32 val; + /* Set USB PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB0_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); +} +#endif diff --git a/configs/am64x_gemini_a53_defconfig b/configs/am64x_gemini_a53_defconfig new file mode 100644 index 0000000000..b3d5e578df --- /dev/null +++ b/configs/am64x_gemini_a53_defconfig @@ -0,0 +1,153 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM642=y +CONFIG_K3_ATF_LOAD_ADDR=0x701c0000 +CONFIG_TARGET_AM642_A53_GEMINI=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am642-gemini-v1" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL" +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_EEPROM is not set +CONFIG_CMD_DM=y +# CONFIG_CMD_GPIO is not set +# CONFIG_CMD_SPI is not set +CONFIG_CMD_DDRSS=y +# CONFIG_CMD_EXT4_WRITE is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_TI_GPMC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y +CONFIG_PHY_CADENCE_SIERRA=y +CONFIG_PHY_CADENCE_TORRENT=y +CONFIG_PHY_J721E_WIZ=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_MEM=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_QSPI_PHY=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LZO=y +CONFIG_HEXDUMP=y diff --git a/configs/am64x_gemini_r5_defconfig b/configs/am64x_gemini_r5_defconfig new file mode 100644 index 0000000000..f65bdd3d48 --- /dev/null +++ b/configs/am64x_gemini_r5_defconfig @@ -0,0 +1,166 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM642=y +CONFIG_TARGET_AM642_R5_GEMINI=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x70000000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x190000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-gemini-v1" +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_TI_GPMC=y +CONFIG_ESM_K3=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HS512T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_QSPI_PHY=y +CONFIG_DM_THERMAL=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/include/configs/am64x_gemini.h b/include/configs/am64x_gemini.h new file mode 100644 index 0000000000..df91709820 --- /dev/null +++ b/include/configs/am64x_gemini.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM642 SoC family + * + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + * Keerthy + */ + +#ifndef __CONFIG_AM642_EVM_H +#define __CONFIG_AM642_EVM_H + +#include +#include +#include +#include +#include + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#ifndef CONFIG_CPU_V7R +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE +#if defined(CONFIG_TARGET_AM642_A53_EVM) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) +#else +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x4000 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location filled in by the boot ROM that we want to read out without any + * interference from the C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (TI_SRAM_SCRATCH_BOARD_EEPROM_START -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#endif + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#define EXTRA_ENV_DFUARGS \ + DFU_ALT_INFO_MMC \ + DFU_ALT_INFO_EMMC_COMBINED \ + DFU_ALT_INFO_RAM + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_FIT_TI_ARGS \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_DFUARGS + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_AM642_EVM_H */