ARM: meson: rename GXBB to GX
Taking into account the Amlogic Family name starts with GX, including the GXBB, GXL and GXM SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
Tom Rini
parent
8b41464547
commit
f0f3762cb7
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@ -0,0 +1,69 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*/
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#ifndef __GX_H__
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#define __GX_H__
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#define GX_FIRMWARE_MEM_SIZE 0x1000000
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#define GX_AOBUS_BASE 0xc8100000
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#define GX_PERIPHS_BASE 0xc8834400
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#define GX_HIU_BASE 0xc883c000
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#define GX_ETH_BASE 0xc9410000
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/* Always-On Peripherals registers */
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#define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2))
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#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)
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#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)
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#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)
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#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95)
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#define GX_AO_MEM_SIZE_MASK 0xFFFF0000
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#define GX_AO_MEM_SIZE_SHIFT 16
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#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
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#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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/* Peripherals registers */
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#define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2))
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/* GPIO registers 0 to 6 */
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#define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
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#define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
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#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
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#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
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#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50)
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#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51)
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#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56)
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#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57)
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#define GX_ETH_REG_0_PHY_INTF BIT(0)
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#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define GX_ETH_REG_0_CLK_EN BIT(12)
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/* HIU registers */
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#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2))
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#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)
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/* Ethernet memory power domain */
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#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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/* Clock gates */
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#define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50)
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#define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51)
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#define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52)
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#define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53)
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#define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54)
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#define GX_GCLK_MPEG_0_I2C BIT(9)
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#define GX_GCLK_MPEG_1_ETH BIT(3)
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#endif /* __GX_H__ */
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@ -1,69 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*/
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#ifndef __GXBB_H__
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#define __GXBB_H__
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#define GXBB_FIRMWARE_MEM_SIZE 0x1000000
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#define GXBB_AOBUS_BASE 0xc8100000
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#define GXBB_PERIPHS_BASE 0xc8834400
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#define GXBB_HIU_BASE 0xc883c000
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#define GXBB_ETH_BASE 0xc9410000
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/* Always-On Peripherals registers */
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#define GXBB_AO_ADDR(off) (GXBB_AOBUS_BASE + ((off) << 2))
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#define GXBB_AO_SEC_GP_CFG0 GXBB_AO_ADDR(0x90)
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#define GXBB_AO_SEC_GP_CFG3 GXBB_AO_ADDR(0x93)
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#define GXBB_AO_SEC_GP_CFG4 GXBB_AO_ADDR(0x94)
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#define GXBB_AO_SEC_GP_CFG5 GXBB_AO_ADDR(0x95)
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#define GXBB_AO_MEM_SIZE_MASK 0xFFFF0000
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#define GXBB_AO_MEM_SIZE_SHIFT 16
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#define GXBB_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
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#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define GXBB_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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/* Peripherals registers */
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#define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
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/* GPIO registers 0 to 6 */
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#define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
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#define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
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#define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
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#define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
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#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
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#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
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#define GXBB_ETH_REG_2 GXBB_PERIPHS_ADDR(0x56)
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#define GXBB_ETH_REG_3 GXBB_PERIPHS_ADDR(0x57)
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#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
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#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define GXBB_ETH_REG_0_CLK_EN BIT(12)
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/* HIU registers */
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#define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2))
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#define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40)
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/* Ethernet memory power domain */
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#define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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/* Clock gates */
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#define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50)
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#define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51)
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#define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52)
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#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
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#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
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#define GXBB_GCLK_MPEG_0_I2C BIT(9)
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#define GXBB_GCLK_MPEG_1_ETH BIT(3)
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#endif /* __GXBB_H__ */
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@ -6,7 +6,7 @@
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#include <common.h>
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#include <linux/libfdt.h>
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#include <linux/err.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/gx.h>
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#include <asm/arch/sm.h>
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#include <asm/armv8/mmu.h>
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#include <asm/unaligned.h>
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@ -39,8 +39,8 @@ int dram_init(void)
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phys_size_t get_effective_memsize(void)
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{
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/* Size is reported in MiB, convert it in bytes */
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return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK)
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>> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M;
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return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
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>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
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}
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static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
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@ -71,27 +71,27 @@ void meson_gx_init_reserved_memory(void *fdt)
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* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
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*/
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reg = readl(GXBB_AO_SEC_GP_CFG3);
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reg = readl(GX_AO_SEC_GP_CFG3);
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bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK)
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>> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
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bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
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bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
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>> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
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bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
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bl31_start = readl(GXBB_AO_SEC_GP_CFG5);
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bl32_start = readl(GXBB_AO_SEC_GP_CFG4);
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bl31_start = readl(GX_AO_SEC_GP_CFG5);
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bl32_start = readl(GX_AO_SEC_GP_CFG4);
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/*
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* Early Meson GXBB Firmware revisions did not provide the reserved
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* Early Meson GX Firmware revisions did not provide the reserved
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* memory zones in the registers, keep fixed memory zone handling.
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*/
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if (IS_ENABLED(CONFIG_MESON_GXBB) &&
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if (IS_ENABLED(CONFIG_MESON_GX) &&
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!reg && !bl31_start && !bl32_start) {
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bl31_start = 0x10000000;
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bl31_size = 0x200000;
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}
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/* Add first 16MiB reserved zone */
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meson_board_add_reserved_memory(fdt, 0, GXBB_FIRMWARE_MEM_SIZE);
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meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
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/* Add BL31 reserved zone */
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if (bl31_start && bl31_size)
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@ -107,7 +107,7 @@ void reset_cpu(ulong addr)
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psci_system_reset();
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}
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static struct mm_region gxbb_mem_map[] = {
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static struct mm_region gx_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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@ -127,4 +127,4 @@ static struct mm_region gxbb_mem_map[] = {
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}
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};
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struct mm_region *mem_map = gxbb_mem_map;
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struct mm_region *mem_map = gx_mem_map;
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@ -7,7 +7,7 @@
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/gx.h>
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#include <asm/arch/eth.h>
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#include <phy.h>
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@ -22,23 +22,23 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* Set RGMII mode */
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setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
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GXBB_ETH_REG_0_TX_PHASE(1) |
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GXBB_ETH_REG_0_TX_RATIO(4) |
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GXBB_ETH_REG_0_PHY_CLK_EN |
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GXBB_ETH_REG_0_CLK_EN);
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setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
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GX_ETH_REG_0_TX_PHASE(1) |
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GX_ETH_REG_0_TX_RATIO(4) |
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GX_ETH_REG_0_PHY_CLK_EN |
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GX_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set RMII mode */
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out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK |
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GXBB_ETH_REG_0_CLK_EN);
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out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
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GX_ETH_REG_0_CLK_EN);
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/* Use GXL RMII Internal PHY */
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if (IS_ENABLED(CONFIG_MESON_GXL) &&
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(flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
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writel(0x10110181, GXBB_ETH_REG_2);
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writel(0xe40908ff, GXBB_ETH_REG_3);
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writel(0x10110181, GX_ETH_REG_2);
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writel(0xe40908ff, GX_ETH_REG_3);
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}
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break;
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@ -49,6 +49,6 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
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}
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/* Enable power and clock gate */
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setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
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clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
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setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH);
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clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
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}
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@ -6,7 +6,7 @@
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*/
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#include <common.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/gx.h>
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#include <linux/kernel.h>
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#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
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@ -8,7 +8,7 @@
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#include <dm.h>
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#include <environment.h>
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#include <asm/io.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/gx.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sm.h>
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#include <asm/arch/eth.h>
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@ -8,7 +8,7 @@
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#include <dm.h>
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#include <environment.h>
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#include <asm/io.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/gx.h>
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#include <asm/arch/sm.h>
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#include <asm/arch/eth.h>
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#include <asm/arch/mem.h>
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@ -33,8 +33,8 @@ int misc_init_r(void)
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MESON_GXL_USE_INTERNAL_RMII_PHY);
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/* Enable power and clock gate */
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setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
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clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
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setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH);
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clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
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if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
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len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
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@ -7,7 +7,7 @@
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#include <dm.h>
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#include <environment.h>
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#include <asm/io.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/gx.h>
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#include <asm/arch/sm.h>
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#include <asm/arch/eth.h>
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#include <asm/arch/mem.h>
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@ -31,13 +31,13 @@ int misc_init_r(void)
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meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
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/* Enable power and clock gate */
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setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C);
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setbits_le32(GX_GCLK_MPEG_0, GX_GCLK_MPEG_0_I2C);
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/* Reset PHY on GPIOZ_14 */
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clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
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clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
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clrbits_le32(GX_GPIO_EN(3), BIT(14));
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clrbits_le32(GX_GPIO_OUT(3), BIT(14));
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mdelay(10);
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setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
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setbits_le32(GX_GPIO_OUT(3), BIT(14));
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if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
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len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
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@ -8,7 +8,7 @@
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#include <dm.h>
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#include <environment.h>
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#include <asm/io.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/gx.h>
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#include <asm/arch/sm.h>
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#include <asm/arch/eth.h>
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#include <asm/arch/mem.h>
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@ -13,6 +13,6 @@
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#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
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#include <configs/meson-gxbb-common.h>
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#include <configs/meson-gx-common.h>
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#endif /* __CONFIG_H */
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@ -13,6 +13,6 @@
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#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
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||||
|
||||
#include <configs/meson-gxbb-common.h>
|
||||
#include <configs/meson-gx-common.h>
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuration for Amlogic Meson GXBB SoCs
|
||||
* Configuration for Amlogic Meson GX SoCs
|
||||
* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __MESON_GXBB_COMMON_CONFIG_H
|
||||
#define __MESON_GXBB_COMMON_CONFIG_H
|
||||
#ifndef __MESON_GX_COMMON_CONFIG_H
|
||||
#define __MESON_GX_COMMON_CONFIG_H
|
||||
|
||||
#define CONFIG_CPU_ARMV8
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
|
@ -43,4 +43,4 @@
|
|||
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */
|
||||
|
||||
#endif /* __MESON_GXBB_COMMON_CONFIG_H */
|
||||
#endif /* __MESON_GX_COMMON_CONFIG_H */
|
||||
|
|
@ -13,6 +13,6 @@
|
|||
|
||||
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0"
|
||||
|
||||
#include <configs/meson-gxbb-common.h>
|
||||
#include <configs/meson-gx-common.h>
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -15,6 +15,6 @@
|
|||
|
||||
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0"
|
||||
|
||||
#include <configs/meson-gxbb-common.h>
|
||||
#include <configs/meson-gx-common.h>
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue