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cache: l2x0: Fix write to incorrect shared-override bit 

The existing code write bit-0 for shared attribute override enable bit.
It should be bit-22 based on cache controller specification [1].

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan 2020-04-17 14:45:35 +08:00 committed by Tom Rini
parent a3d7cb1939
commit f62782fb29
1 changed files with 2 additions and 2 deletions
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4
drivers/cache/cache-l2x0.c vendored
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@ -33,8 +33,8 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK; saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
} }
saved_reg |= dev_read_bool(dev, "arm,shared-override"); if (dev_read_bool(dev, "arm,shared-override"))
writel(saved_reg, &regs->pl310_aux_ctrl); saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE;
saved_reg = readl(&regs->pl310_tag_latency_ctrl); saved_reg = readl(&regs->pl310_tag_latency_ctrl);
if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))