hancock: ethernet support
This commit is contained in:
Rene Straub
parent
9d93827bdb
commit
f69a6aff24
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@ -16,6 +16,7 @@
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk_synthesizer.h>
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@ -38,6 +39,7 @@
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#include "../common/board_descriptor.h"
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#include "board.h"
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#include "da9063.h"
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#include "sja1105.h"
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#include "fileaccess.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -141,6 +143,22 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static BD_Context bdctx[3]; /* The descriptor contexts */
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#if !defined(CONFIG_SPL_BUILD)
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/* SPI1 */
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static struct module_pin_mux spi1_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), (MODE(4) | PULLUDEN | PULLDOWN_EN | RXACTIVE)}, /* (C18) spi1_clk */
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{OFFSET(uart0_rtsn), (MODE(4) | PULLUDEN | PULLUP_EN)}, /* (E17) spi1_mosi */
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{OFFSET(uart0_ctsn), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (E18) spi1_miso */
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{OFFSET(uart0_txd), (MODE(1) | PULLUDEN | PULLUP_EN)}, /* (E16) spi1_cs1 */
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{-1}
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#if 0
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{OFFSET(uart0_rxd), (MODE(1) | PULLUDEN | PULLUP_EN)}, /* (E15) spi1_cs0 */
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#endif
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};
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static struct spi_slave *spi = 0;
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#endif
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static void request_and_set_gpio(int gpio, const char *name, int value)
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{
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@ -287,7 +305,7 @@ struct serial_device *default_serial_console(void)
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/* TODO: Remove later */
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enable_uart2_pin_mux();
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return &eserial3_device;
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#if 0
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if (spl_boot_device() == BOOT_DEVICE_UART) {
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/* SPL Boot -> UART0 (later used for SPI) */
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enable_uart0_pin_mux();
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@ -298,6 +316,7 @@ struct serial_device *default_serial_console(void)
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enable_uart2_pin_mux();
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return &eserial3_device;
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}
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#endif
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}
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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@ -499,6 +518,50 @@ static void init_gnss(void)
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REQUEST_AND_SET_GPIO(GPIO_RST_GNSS);
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}
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static void init_ethernet_switch(void)
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{
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uint32_t val;
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if (spi == 0) {
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configure_module_pin_mux(spi1_pin_mux);
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spi_init();
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spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS /*bus*/,
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CONFIG_SJA1105_SPI_CS /*cs*/,
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1000000 /*max_hz*/,
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SPI_MODE_1 /*spi_mode*/);
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/* spi_set_wordlen(spi,32);*/
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}
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spi_claim_bus(spi);
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/* TODO: Remove debug printout later on */
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val = sja1105_read_reg(spi, 0x000000);
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printf("Device ID: %08x\n", val);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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sja1105_static_init(spi, 0 /*dummy*/);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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/* TODO: Check valid config bit */
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/* Configure clocks */
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sja1105_dynamic_init(spi);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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/* Enable pull down on RX_ER etc. */
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sja1105_write_reg(spi, 0x100809, 0x03020313);
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#if 0
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val = sja1105_read_reg(spi, 0x100809);
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printf("CFG_PAD_MII4_RX Reg: %08x\n", val);
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#endif
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spi_release_bus(spi);
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}
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#endif /* !defined(CONFIG_SPL_BUILD) */
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@ -571,6 +634,7 @@ void set_console(void)
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#endif
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}
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#if 0
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static void set_devicetree_name(void)
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{
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char devicetreename[64];
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@ -664,7 +728,7 @@ static void check_reset_button(void)
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if (!get_button_state())
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break;
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udelay(100*1000); /* 100ms */
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2 udelay(100*1000); /* 100ms */
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counter += 100;
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if (counter == 2000) {
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@ -709,6 +773,8 @@ static void check_reset_button(void)
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/* setenv("consoledev", "ttyS1"); */
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}
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}
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#endif
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#endif /* !defined(CONFIG_SPL_BUILD) */
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@ -740,8 +806,6 @@ int board_late_init(void)
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init_gsm();
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init_gnss();
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printf("Console: %d\n", CONFIG_CONS_INDEX);
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/* TODO: Change for battery operation */
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/* Enable charging of RTC backup capacitor (1mA, 3.1V) */
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/*(void)da9063_set_reg(PMIC_REG_BBAT_CONT, 0xCF);*/
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@ -758,6 +822,10 @@ int board_late_init(void)
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/*
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check_fct();
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*/
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init_ethernet_switch();
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#endif
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return 0;
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@ -780,7 +848,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_if = PHY_INTERFACE_MODE_RMII,
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.phy_addr = 0
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.phy_addr = 1
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}
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};
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@ -841,7 +909,6 @@ int board_eth_init(bd_t *bis)
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#if !defined(CONFIG_SPL_BUILD)
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#ifdef CONFIG_DRIVER_TI_CPSW
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cpsw_data.mdio_div = 0x3E;
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bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
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@ -886,25 +953,10 @@ int board_fit_config_name_match(const char *name)
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#if !defined(CONFIG_SPL_BUILD)
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#include <asm/arch/mux.h>
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/* SPI1 */
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static struct module_pin_mux spi1_pin_mux[] = {
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{OFFSET(ecap0_in_pwm0_out), (MODE(4) | PULLUDEN | PULLDOWN_EN)}, /* (C18) spi1_clk */
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{OFFSET(uart0_rtsn), (MODE(4) | PULLUDEN | PULLUP_EN)}, /* (E17) spi1_mosi */
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{OFFSET(uart0_ctsn), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (E18) spi1_miso */
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{OFFSET(uart0_txd), (MODE(1) | PULLUDEN | PULLUP_EN)}, /* (E16) spi1_cs1 */
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{-1}
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#if 0
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{OFFSET(uart0_rxd), (MODE(1) | PULLUDEN | PULLUP_EN)}, /* (E15) spi1_cs0 */
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#endif
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};
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static struct spi_slave *spi = 0;
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static int do_spitest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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const uint8_t data[] = { 0xFF, 0xAA, 0x00 };
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/* const uint8_t data[] = { 0xFF, 0xAA, 0x00 };*/
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const uint8_t data[] = { 0xAA, 0x55, 0xAA, 0x55, 0x00, 0xFF };
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int rc;
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printf("SPI test\n");
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@ -941,5 +993,93 @@ U_BOOT_CMD(
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""
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);
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static int do_sjastart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uint32_t val;
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if (spi == 0) {
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configure_module_pin_mux(spi1_pin_mux);
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spi_init();
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spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS /*bus*/,
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CONFIG_SJA1105_SPI_CS /*cs*/,
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1000000 /*max_hz*/,
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SPI_MODE_1 /*spi_mode*/);
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/* spi_set_wordlen(spi,32);*/
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}
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spi_claim_bus(spi);
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val = sja1105_read_reg(spi, 0x000000);
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printf("Device ID: %08x\n", val);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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sja1105_static_init(spi, 0 /*dummy*/);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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sja1105_dynamic_init(spi);
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val = sja1105_read_reg(spi, 0x000001);
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printf("Status Reg: %08x\n", val);
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spi_release_bus(spi);
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return 0;
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}
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U_BOOT_CMD(
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sjastart, 1, 1, do_sjastart,
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"start and configure ETH switch",
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""
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);
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static int do_sjainfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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uint32_t p3_mac_stat;
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uint32_t p3_txf;
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uint32_t p3_rxf;
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uint32_t p4_mac_stat;
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uint32_t p4_rxf;
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uint32_t p4_txf;
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uint32_t conf_pad4_1;
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uint32_t conf_pad4_2;
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spi_claim_bus(spi);
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p3_mac_stat = sja1105_read_reg(spi, 0x00206);
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p3_rxf = sja1105_read_reg(spi, 0x00436);
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p3_txf = sja1105_read_reg(spi, 0x00432);
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p4_mac_stat = sja1105_read_reg(spi, 0x00208);
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p4_rxf = sja1105_read_reg(spi, 0x00446);
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p4_txf = sja1105_read_reg(spi, 0x00442);
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conf_pad4_1 = sja1105_read_reg(spi, 0x100809);
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sja1105_write_reg(spi, 0x100809, 0x03020313);
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conf_pad4_2 = sja1105_read_reg(spi, 0x100809);
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spi_release_bus(spi);
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printf("port mac stat rx tx\n");
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printf("3 (PHY): %08x %d %d\n", p3_mac_stat, p3_rxf, p3_txf);
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printf("4 (CPU): %08x %d %d\n", p4_mac_stat, p4_rxf, p4_txf);
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printf("pad: %08x\n", conf_pad4_1);
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printf("pad: %08x\n", conf_pad4_2);
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return 0;
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}
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U_BOOT_CMD(
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sjainfo, 1, 1, do_sjainfo,
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"display eth switch information",
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""
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);
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#endif
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@ -15,7 +15,7 @@
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#define SJA_OPCODE_WRITE 0x80
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#define SJA_OPCODE_READ 0x00
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/*#define SJA_READ_CNT(x) (((x) &0x3F) << 1)*/
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/*#define SJA_READ_CNT(x) (((x) & 0x3F) << 1)*/
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/*
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@ -71,7 +71,7 @@ int sja1105_read_reg(struct spi_slave *spislave, uint32_t adress)
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{
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uint8_t dataspi[8];
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uint8_t datain[8];
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int rc;
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/* int rc; */
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int return_value;
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/* OPCODE: READ, READ CNT = 1 */
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@ -87,10 +87,9 @@ int sja1105_read_reg(struct spi_slave *spislave, uint32_t adress)
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/* printf("%02x %02x %02x %02x\n", dataspi[0], dataspi[1], dataspi[2], dataspi[3]); */
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memset(datain, 0xaa, 8);
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rc = spi_xfer(spislave, 8*sizeof(dataspi) /*bitlen*/, dataspi, datain /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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printf("sja1105_read_reg %d\n", rc);
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(void)spi_xfer(spislave, 8*sizeof(dataspi) /*bitlen*/, dataspi, datain /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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/*
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printf("sja1105_read_reg %d\n", rc);
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printf("%02x %02x %02x %02x\n", datain[0], datain[1], datain[2], datain[3]);
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printf("%02x %02x %02x %02x\n", datain[4], datain[5], datain[6], datain[7]);
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*/
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@ -143,7 +142,10 @@ void sja1105_dynamic_init(struct spi_slave *spislave)
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rc = sja1105_write_reg(spislave, 0x10000F, 0x0A000001); //Disable IDIV4
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rc = sja1105_write_reg(spislave, 0x100031, 0x08000800); //Setting CLKSRC of RMII_REF_CLK_4 to TX_CLK_4
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printf("%d\n", rc);
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/* TODO: remove */
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(void)rc;
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/* printf("%d\n", rc); */
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}
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