tegra: Correct tegra124 clock name
The first clock type appears to have and incorrect setting for out of the mux outputs. It should be CLK_M, not OSC. Fix it and its only user. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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				|  | @ -71,7 +71,7 @@ enum { | |||
|  */ | ||||
| #define CLK(x) CLOCK_ID_ ## x | ||||
| static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { | ||||
| 	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC), | ||||
| 	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(CLK_M), | ||||
| 		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE), | ||||
| 		MASK_BITS_31_30}, | ||||
| 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO), | ||||
|  |  | |||
|  | @ -121,7 +121,7 @@ static void enable_required_clocks(void) | |||
| int nvidia_board_init(void) | ||||
| { | ||||
| 	clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000); | ||||
| 	clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000); | ||||
| 	clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000); | ||||
| 
 | ||||
| 	/* For external MAX98090 audio codec */ | ||||
| 	clock_external_output(1); | ||||
|  |  | |||
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