MLK-20163-03 board: imx8mq_evk: Refact the imx8mq dram init code
Refact the i.MX8MQ dram init flow to reuse the common dram driver used by i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com>
This commit is contained in:
Bai Ping
Nitin Garg
parent
cb43368096
commit
f773733d4a
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@ -21,6 +21,7 @@ config TARGET_IMX8MQ_EVK
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bool "imx8mq_evk"
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bool "imx8mq_evk"
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select IMX8MQ
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select IMX8MQ
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select SUPPORT_SPL
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select SUPPORT_SPL
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select IMX8M_LPDDR4
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config TARGET_IMX8MQ_DDR3L_ARM2
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config TARGET_IMX8MQ_DDR3L_ARM2
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bool "imx8mq_ddr3l_arm2"
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bool "imx8mq_ddr3l_arm2"
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@ -8,5 +8,5 @@ obj-y += imx8mq_evk.o
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-y += spl.o
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obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
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obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
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endif
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endif
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@ -1,34 +0,0 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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enum fw_type {
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FW_1D_IMAGE,
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FW_2D_IMAGE,
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};
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void ddr_init(void);
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void ddr_load_train_code(enum fw_type type);
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void lpddr4_800M_cfg_phy(void);
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static inline void reg32_write(unsigned long addr, u32 val)
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{
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writel(val, addr);
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}
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static inline uint32_t reg32_read(unsigned long addr)
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{
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return readl(addr);
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}
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static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
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{
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writel(val, addr);
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}
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static inline void reg32setbit(unsigned long addr, u32 bit)
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{
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setbits_le32(addr, (1 << bit));
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}
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@ -1,275 +0,0 @@
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/*
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* Copyright 2017-2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include "ddr.h"
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#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
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#define ddr_printf(args...) printf(args)
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#else
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#define ddr_printf(args...)
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#endif
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#include "wait_ddrphy_training_complete.c"
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#ifndef SRC_DDRC_RCR_ADDR
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#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
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#endif
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#ifndef DDR_CSD1_BASE_ADDR
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#define DDR_CSD1_BASE_ADDR 0x40000000
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#endif
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#define SILICON_TRAIN
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#define DDR_BOOT_P1 /* default DDR boot frequency point */
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#define WR_POST_EXT_3200
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volatile unsigned int tmp, tmp_t, i;
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void lpddr4_800MHz_cfg_umctl2(void)
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{
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/* Start to config, default 3200mbps */
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/* dis_dq=1, indicates no reads or writes are issued to SDRAM */
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reg32_write(DDRC_DBG1(0), 0x00000001);
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/* selfref_en=1, SDRAM enter self-refresh state */
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reg32_write(DDRC_PWRCTL(0), 0x00000001);
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reg32_write(DDRC_MSTR(0), 0xa3080020);
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reg32_write(DDRC_MSTR2(0), 0x00000000);
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reg32_write(DDRC_RFSHTMG(0), 0x006100E0);
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reg32_write(DDRC_INIT0(0), 0xC003061B);
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reg32_write(DDRC_INIT1(0), 0x009D0000);
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reg32_write(DDRC_INIT3(0), 0x00D4002D);
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#ifdef WR_POST_EXT_3200 // recommened to define
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reg32_write(DDRC_INIT4(0), 0x00330008);
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#else
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reg32_write(DDRC_INIT4(0), 0x00310008);
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#endif
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reg32_write(DDRC_INIT6(0), 0x0066004a);
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reg32_write(DDRC_INIT7(0), 0x0006004a);
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reg32_write(DDRC_DRAMTMG0(0), 0x1A201B22);
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reg32_write(DDRC_DRAMTMG1(0), 0x00060633);
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reg32_write(DDRC_DRAMTMG3(0), 0x00C0C000);
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reg32_write(DDRC_DRAMTMG4(0), 0x0F04080F);
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reg32_write(DDRC_DRAMTMG5(0), 0x02040C0C);
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reg32_write(DDRC_DRAMTMG6(0), 0x01010007);
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reg32_write(DDRC_DRAMTMG7(0), 0x00000401);
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reg32_write(DDRC_DRAMTMG12(0), 0x00020600);
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reg32_write(DDRC_DRAMTMG13(0), 0x0C100002);
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reg32_write(DDRC_DRAMTMG14(0), 0x000000E6);
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reg32_write(DDRC_DRAMTMG17(0), 0x00A00050);
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reg32_write(DDRC_ZQCTL0(0), 0x03200018);
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reg32_write(DDRC_ZQCTL1(0), 0x028061A8);
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reg32_write(DDRC_ZQCTL2(0), 0x00000000);
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reg32_write(DDRC_DFITMG0(0), 0x0497820A);
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reg32_write(DDRC_DFITMG1(0), 0x00080303);
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reg32_write(DDRC_DFIUPD0(0), 0xE0400018);
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reg32_write(DDRC_DFIUPD1(0), 0x00DF00E4);
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reg32_write(DDRC_DFIUPD2(0), 0x80000000);
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reg32_write(DDRC_DFIMISC(0), 0x00000011);
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reg32_write(DDRC_DFITMG2(0), 0x0000170A);
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reg32_write(DDRC_DBICTL(0), 0x00000001);
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reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
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/* need be refined by ddrphy trained value */
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reg32_write(DDRC_RANKCTL(0), 0x00000c99);
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reg32_write(DDRC_DRAMTMG2(0), 0x070E171a);
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/* address mapping */
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/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
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reg32_write(DDRC_ADDRMAP0(0), 0x00000015);
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reg32_write(DDRC_ADDRMAP3(0), 0x00000000);
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/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
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reg32_write(DDRC_ADDRMAP4(0), 0x00001F1F);
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/* bank interleave */
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/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
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reg32_write(DDRC_ADDRMAP1(0), 0x00080808);
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/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
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reg32_write(DDRC_ADDRMAP5(0), 0x07070707);
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/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
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reg32_write(DDRC_ADDRMAP6(0), 0x08080707);
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/* 667mts frequency setting */
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reg32_write(DDRC_FREQ1_DERATEEN(0), 0x0000000);
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reg32_write(DDRC_FREQ1_DERATEINT(0), 0x0800000);
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reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0210000);
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reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x014001E);
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reg32_write(DDRC_FREQ1_INIT3(0), 0x0140009);
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reg32_write(DDRC_FREQ1_INIT4(0), 0x00310008);
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reg32_write(DDRC_FREQ1_INIT6(0), 0x0066004a);
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reg32_write(DDRC_FREQ1_INIT7(0), 0x0006004a);
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reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0xB070A07);
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reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x003040A);
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reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x305080C);
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reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x0505000);
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reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x3040203);
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reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x2030303);
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reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x2020004);
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reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000302);
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reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x0020310);
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reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0xA100002);
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reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x0000020);
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reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0220011);
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reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x0A70005);
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reg32_write(DDRC_FREQ1_DFITMG0(0), 0x3858202);
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reg32_write(DDRC_FREQ1_DFITMG1(0), 0x0000404);
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reg32_write(DDRC_FREQ1_DFITMG2(0), 0x0000502);
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/* performance setting */
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dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
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dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
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dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
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dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
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/* 150T starve and 0x90 max tran len */
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dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x90000096);
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/* 300T starve and 0x10 max tran len */
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dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x1000012c);
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dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
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dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
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dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
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dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
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dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
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dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
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/* disable Read Qos*/
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dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x00000e00);
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dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x0062ffff);
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/* disable Write Qos*/
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dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00000e00);
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dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000ffff);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
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}
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void ddr_init(void)
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{
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
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mdelay(100);
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
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/* change the clock source of dram_apb_clk_root */
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reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1), (0x7<<24)|(0x7<<16));
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reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1), (0x4<<24)|(0x3<<16));
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/* disable iso */
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reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
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reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
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dram_pll_init(SSCG_PLL_OUT_800M);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
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/* Configure uMCTL2's registers */
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lpddr4_800MHz_cfg_umctl2();
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#ifdef DDR_BOOT_P2
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reg32_write(DDRC_MSTR2(0), 0x2);
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#else
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#ifdef DDR_BOOT_P1
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reg32_write(DDRC_MSTR2(0), 0x1);
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#endif
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#endif
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/* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
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/* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
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reg32_write(DDRC_DBG1(0), 0x00000000);
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tmp = reg32_read(DDRC_PWRCTL(0));
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reg32_write(DDRC_PWRCTL(0), 0x000000a8);
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while ((reg32_read(DDRC_STAT(0)) & 0x33f) != 0x223)
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;
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* LPDDR4 mode */
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reg32_write(DDRC_DDR_SS_GPR0, 0x01);
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#ifdef DDR_BOOT_P1
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reg32_write(DDRC_DFIMISC(0), 0x00000110);
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#else
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reg32_write(DDRC_DFIMISC(0), 0x00000010);
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#endif
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/* LPDDR4 PHY config and training */
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lpddr4_800M_cfg_phy();
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reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
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reg32_write(DDRC_SWCTL(0), 0x0000);
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/* Set DFIMISC.dfi_init_start to 1 */
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#ifdef DDR_BOOT_P2
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reg32_write(DDRC_DFIMISC(0), 0x00000230);
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#else
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#ifdef DDR_BOOT_P1
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reg32_write(DDRC_DFIMISC(0), 0x00000130);
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#else
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reg32_write(DDRC_DFIMISC(0), 0x00000030);
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#endif
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#endif
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reg32_write(DDRC_SWCTL(0), 0x0001);
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/* wait DFISTAT.dfi_init_complete to 1 */
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while ((reg32_read(DDRC_DFISTAT(0)) & 0x1) == 0x0)
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;
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reg32_write(DDRC_SWCTL(0), 0x0000);
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#ifdef DDR_BOOT_P2
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reg32_write(DDRC_DFIMISC(0), 0x00000210);
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/* set DFIMISC.dfi_init_complete_en again */
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reg32_write(DDRC_DFIMISC(0), 0x00000211);
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#else
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#ifdef DDR_BOOT_P1
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reg32_write(DDRC_DFIMISC(0), 0x00000110);
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/* set DFIMISC.dfi_init_complete_en again */
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|
||||||
reg32_write(DDRC_DFIMISC(0), 0x00000111);
|
|
||||||
#else
|
|
||||||
/* clear DFIMISC.dfi_init_complete_en */
|
|
||||||
reg32_write(DDRC_DFIMISC(0), 0x00000010);
|
|
||||||
/* set DFIMISC.dfi_init_complete_en again */
|
|
||||||
reg32_write(DDRC_DFIMISC(0), 0x00000011);
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
reg32_write(DDRC_PWRCTL(0), 0x00000088);
|
|
||||||
|
|
||||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
|
||||||
|
|
||||||
/*
|
|
||||||
* set SWCTL.sw_done to enable quasi-dynamic register
|
|
||||||
* programming outside reset.
|
|
||||||
*/
|
|
||||||
reg32_write(DDRC_SWCTL(0), 0x00000001);
|
|
||||||
|
|
||||||
/* wait SWSTAT.sw_done_ack to 1 */
|
|
||||||
while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0x0)
|
|
||||||
;
|
|
||||||
|
|
||||||
/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
|
|
||||||
while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
|
|
||||||
;
|
|
||||||
|
|
||||||
reg32_write(DDRC_PWRCTL(0), 0x00000088);
|
|
||||||
|
|
||||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
|
||||||
|
|
||||||
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
|
|
||||||
|
|
||||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
|
||||||
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
|
|
||||||
}
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,104 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2017 NXP
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <spl.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <errno.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/arch/ddr.h>
|
|
||||||
#include <asm/sections.h>
|
|
||||||
|
|
||||||
#include "ddr.h"
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
#define IMEM_LEN 32768//23400 //byte
|
|
||||||
#define DMEM_LEN 16384//1720 //byte
|
|
||||||
#define IMEM_2D_OFFSET 49152
|
|
||||||
|
|
||||||
#define IMEM_OFFSET_ADDR 0x00050000
|
|
||||||
#define DMEM_OFFSET_ADDR 0x00054000
|
|
||||||
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
|
|
||||||
|
|
||||||
/* We need PHY iMEM PHY is 32KB padded */
|
|
||||||
void ddr_load_train_code(enum fw_type type)
|
|
||||||
{
|
|
||||||
u32 tmp32, i;
|
|
||||||
u32 error = 0;
|
|
||||||
unsigned long pr_to32, pr_from32;
|
|
||||||
unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
|
|
||||||
unsigned long imem_start = (unsigned long)&_end + fw_offset;
|
|
||||||
unsigned long dmem_start = imem_start + IMEM_LEN;
|
|
||||||
|
|
||||||
pr_from32 = imem_start;
|
|
||||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
|
|
||||||
for(i = 0x0; i < IMEM_LEN; ){
|
|
||||||
tmp32 = readl(pr_from32);
|
|
||||||
writew(tmp32 & 0x0000ffff, pr_to32);
|
|
||||||
pr_to32 += 4;
|
|
||||||
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
|
|
||||||
pr_to32 += 4;
|
|
||||||
pr_from32 += 4;
|
|
||||||
i += 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
pr_from32 = dmem_start;
|
|
||||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
|
|
||||||
for(i = 0x0; i < DMEM_LEN;){
|
|
||||||
tmp32 = readl(pr_from32);
|
|
||||||
writew(tmp32 & 0x0000ffff, pr_to32);
|
|
||||||
pr_to32 += 4;
|
|
||||||
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
|
|
||||||
pr_to32 += 4;
|
|
||||||
pr_from32 += 4;
|
|
||||||
i += 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
printf("check ddr4_pmu_train_imem code\n");
|
|
||||||
pr_from32 = imem_start;
|
|
||||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
|
|
||||||
for(i = 0x0; i < IMEM_LEN;){
|
|
||||||
tmp32 = (readw(pr_to32) & 0x0000ffff);
|
|
||||||
pr_to32 += 4;
|
|
||||||
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
|
|
||||||
|
|
||||||
if(tmp32 != readl(pr_from32)){
|
|
||||||
printf("%lx %lx\n", pr_from32, pr_to32);
|
|
||||||
error++;
|
|
||||||
}
|
|
||||||
pr_from32 += 4;
|
|
||||||
pr_to32 += 4;
|
|
||||||
i += 4;
|
|
||||||
}
|
|
||||||
if(error){
|
|
||||||
printf("check ddr4_pmu_train_imem code fail=%d\n",error);
|
|
||||||
}else{
|
|
||||||
printf("check ddr4_pmu_train_imem code pass\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
printf("check ddr4_pmu_train_dmem code\n");
|
|
||||||
pr_from32 = dmem_start;
|
|
||||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
|
|
||||||
for(i = 0x0; i < DMEM_LEN;){
|
|
||||||
tmp32 = (readw(pr_to32) & 0x0000ffff);
|
|
||||||
pr_to32 += 4;
|
|
||||||
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
|
|
||||||
if(tmp32 != readl(pr_from32)){
|
|
||||||
printf("%lx %lx\n", pr_from32, pr_to32);
|
|
||||||
error++;
|
|
||||||
}
|
|
||||||
pr_from32 += 4;
|
|
||||||
pr_to32 += 4;
|
|
||||||
i += 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
if(error){
|
|
||||||
printf("check ddr4_pmu_train_dmem code fail=%d",error);
|
|
||||||
}else{
|
|
||||||
printf("check ddr4_pmu_train_dmem code pass\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -1,78 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2018 NXP
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __LPDDR4_DVFS_H__
|
|
||||||
#define __LPDDR4_DVFS_H__
|
|
||||||
#include <asm/arch/ddr.h>
|
|
||||||
|
|
||||||
#define DFILP_SPT
|
|
||||||
|
|
||||||
#define ANAMIX_PLL_BASE_ADDR 0x30360000
|
|
||||||
#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
|
|
||||||
#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
|
|
||||||
#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
|
|
||||||
|
|
||||||
#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */
|
|
||||||
#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */
|
|
||||||
#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */
|
|
||||||
#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */
|
|
||||||
|
|
||||||
/* 2D share & weight */
|
|
||||||
#define LPDDR4_2D_WEIGHT 0x1f7f
|
|
||||||
#define LPDDR4_2D_SHARE 1
|
|
||||||
#define LPDDR4_CATRAIN_3200_1d 0
|
|
||||||
#define LPDDR4_CATRAIN_400 0
|
|
||||||
#define LPDDR4_CATRAIN_100 0
|
|
||||||
#define LPDDR4_CATRAIN_3200_2d 0
|
|
||||||
|
|
||||||
#define WR_POST_EXT_3200 /* recommened to define */
|
|
||||||
|
|
||||||
/* lpddr4 phy training config */
|
|
||||||
/* for LPDDR4 Rtt */
|
|
||||||
#define LPDDR4_RTT40 6
|
|
||||||
#define LPDDR4_RTT48 5
|
|
||||||
#define LPDDR4_RTT60 4
|
|
||||||
#define LPDDR4_RTT80 3
|
|
||||||
#define LPDDR4_RTT120 2
|
|
||||||
#define LPDDR4_RTT240 1
|
|
||||||
#define LPDDR4_RTT_DIS 0
|
|
||||||
|
|
||||||
/* for LPDDR4 Ron */
|
|
||||||
#define LPDDR4_RON34 7
|
|
||||||
#define LPDDR4_RON40 6
|
|
||||||
#define LPDDR4_RON48 5
|
|
||||||
#define LPDDR4_RON60 4
|
|
||||||
#define LPDDR4_RON80 3
|
|
||||||
|
|
||||||
#define LPDDR4_PHY_ADDR_RON60 0x1
|
|
||||||
#define LPDDR4_PHY_ADDR_RON40 0x3
|
|
||||||
#define LPDDR4_PHY_ADDR_RON30 0x7
|
|
||||||
#define LPDDR4_PHY_ADDR_RON24 0xf
|
|
||||||
#define LPDDR4_PHY_ADDR_RON20 0x1f
|
|
||||||
|
|
||||||
/* for read channel */
|
|
||||||
#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */
|
|
||||||
#define LPDDR4_PHY_RTT 30
|
|
||||||
#define LPDDR4_PHY_VREF_VALUE 17
|
|
||||||
|
|
||||||
/* for write channel */
|
|
||||||
#define LPDDR4_PHY_RON 30
|
|
||||||
#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
|
|
||||||
#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */
|
|
||||||
#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */
|
|
||||||
#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */
|
|
||||||
#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */
|
|
||||||
#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */
|
|
||||||
#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */
|
|
||||||
#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */
|
|
||||||
#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
|
|
||||||
#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
|
|
||||||
#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */
|
|
||||||
|
|
||||||
#define LPDDR4_2D_WEIGHT 0x1f7f
|
|
||||||
#define LPDDR4_2D_SHARE 1
|
|
||||||
|
|
||||||
#endif /*__LPDDR4_DVFS_H__ */
|
|
||||||
|
|
@ -1,96 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2017 NXP
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
static inline void poll_pmu_message_ready(void)
|
|
||||||
{
|
|
||||||
unsigned int reg;
|
|
||||||
|
|
||||||
do {
|
|
||||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
|
|
||||||
} while (reg & 0x1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void ack_pmu_message_recieve(void)
|
|
||||||
{
|
|
||||||
unsigned int reg;
|
|
||||||
|
|
||||||
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
|
|
||||||
|
|
||||||
do {
|
|
||||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
|
|
||||||
} while (!(reg & 0x1));
|
|
||||||
|
|
||||||
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline unsigned int get_mail(void)
|
|
||||||
{
|
|
||||||
unsigned int reg;
|
|
||||||
|
|
||||||
poll_pmu_message_ready();
|
|
||||||
|
|
||||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
|
|
||||||
|
|
||||||
ack_pmu_message_recieve();
|
|
||||||
|
|
||||||
return reg;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline unsigned int get_stream_message(void)
|
|
||||||
{
|
|
||||||
unsigned int reg, reg2;
|
|
||||||
|
|
||||||
poll_pmu_message_ready();
|
|
||||||
|
|
||||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
|
|
||||||
|
|
||||||
reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
|
|
||||||
|
|
||||||
reg2 = (reg2 << 16) | reg;
|
|
||||||
|
|
||||||
ack_pmu_message_recieve();
|
|
||||||
|
|
||||||
return reg2;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void decode_major_message(unsigned int mail)
|
|
||||||
{
|
|
||||||
ddr_printf("[PMU Major message = 0x%08x]\n", mail);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void decode_streaming_message(void)
|
|
||||||
{
|
|
||||||
unsigned int string_index, arg __maybe_unused;
|
|
||||||
int i = 0;
|
|
||||||
|
|
||||||
string_index = get_stream_message();
|
|
||||||
ddr_printf(" PMU String index = 0x%08x\n", string_index);
|
|
||||||
while (i < (string_index & 0xffff)){
|
|
||||||
arg = get_stream_message();
|
|
||||||
ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
|
|
||||||
i++;
|
|
||||||
}
|
|
||||||
|
|
||||||
ddr_printf("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
void wait_ddrphy_training_complete(void)
|
|
||||||
{
|
|
||||||
unsigned int mail;
|
|
||||||
while (1) {
|
|
||||||
mail = get_mail();
|
|
||||||
decode_major_message(mail);
|
|
||||||
if (mail == 0x08) {
|
|
||||||
decode_streaming_message();
|
|
||||||
} else if (mail == 0x07) {
|
|
||||||
printf("Training PASS\n");
|
|
||||||
break;
|
|
||||||
} else if (mail == 0xff) {
|
|
||||||
printf("Training FAILED\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -21,14 +21,19 @@
|
||||||
#include <asm/mach-imx/mxc_i2c.h>
|
#include <asm/mach-imx/mxc_i2c.h>
|
||||||
#include <fsl_esdhc.h>
|
#include <fsl_esdhc.h>
|
||||||
#include <mmc.h>
|
#include <mmc.h>
|
||||||
#include "ddr/ddr.h"
|
#include <asm/arch/imx8m_ddr.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
extern struct dram_timing_info dram_timing_b0;
|
||||||
|
|
||||||
void spl_dram_init(void)
|
void spl_dram_init(void)
|
||||||
{
|
{
|
||||||
/* ddr init */
|
/* ddr init */
|
||||||
ddr_init();
|
if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
|
||||||
|
ddr_init(&dram_timing);
|
||||||
|
else
|
||||||
|
ddr_init(&dram_timing_b0);
|
||||||
}
|
}
|
||||||
|
|
||||||
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
||||||
|
|
|
||||||
|
|
@ -3,6 +3,7 @@ CONFIG_ARCH_IMX8M=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||||
CONFIG_TARGET_IMX8MQ_EVK=y
|
CONFIG_TARGET_IMX8MQ_EVK=y
|
||||||
|
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_SUPPORT"
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_SUPPORT"
|
||||||
CONFIG_EFI_PARTITION=y
|
CONFIG_EFI_PARTITION=y
|
||||||
CONFIG_ARCH_MISC_INIT=y
|
CONFIG_ARCH_MISC_INIT=y
|
||||||
|
|
|
||||||
|
|
@ -3,6 +3,7 @@ CONFIG_ARCH_IMX8M=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||||
CONFIG_TARGET_IMX8MQ_EVK=y
|
CONFIG_TARGET_IMX8MQ_EVK=y
|
||||||
|
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_THINGS_SUPPORT"
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,ANDROID_THINGS_SUPPORT"
|
||||||
CONFIG_EFI_PARTITION=y
|
CONFIG_EFI_PARTITION=y
|
||||||
CONFIG_ARCH_MISC_INIT=y
|
CONFIG_ARCH_MISC_INIT=y
|
||||||
|
|
|
||||||
|
|
@ -3,6 +3,7 @@ CONFIG_ARCH_IMX8M=y
|
||||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||||
CONFIG_TARGET_IMX8MQ_EVK=y
|
CONFIG_TARGET_IMX8MQ_EVK=y
|
||||||
|
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
|
||||||
CONFIG_ARCH_MISC_INIT=y
|
CONFIG_ARCH_MISC_INIT=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue