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Merge branch 'master' of git://git.denx.de/u-boot-mmc

This commit is contained in:
Tom Rini 2013-07-16 21:05:35 -04:00
parent 2a6936059a a61da72bda
commit f78cb2ab1e
2 changed files with 4 additions and 5 deletions
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1
drivers/mmc/dw_mmc.c
View File

@ -23,7 +23,6 @@
#include <malloc.h> #include <malloc.h>
#include <mmc.h> #include <mmc.h>
#include <dwmmc.h> #include <dwmmc.h>
#include <asm/arch/clk.h>
#include <asm-generic/errno.h> #include <asm-generic/errno.h>
#define PAGE_SIZE 4096 #define PAGE_SIZE 4096

8
drivers/mmc/fsl_esdhc.c
View File

@ -100,7 +100,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
else if (cmd->resp_type & MMC_RSP_PRESENT) else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48; xfertyp |= XFERTYP_RSPTYP_48;
#ifdef CONFIG_MX53 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT; xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif #endif
@ -470,7 +470,7 @@ static int esdhc_init(struct mmc *mmc)
int timeout = 1000; int timeout = 1000;
/* Reset the entire host controller */ /* Reset the entire host controller */
esdhc_write32(&regs->sysctl, SYSCTL_RSTA); esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
/* Wait until the controller is available */ /* Wait until the controller is available */
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
@ -481,7 +481,7 @@ static int esdhc_init(struct mmc *mmc)
esdhc_write32(&regs->scr, 0x00000040); esdhc_write32(&regs->scr, 0x00000040);
#endif #endif
esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */ /* Set the initial clock speed */
mmc_set_clock(mmc, 400000); mmc_set_clock(mmc, 400000);
@ -515,7 +515,7 @@ static void esdhc_reset(struct fsl_esdhc *regs)
unsigned long timeout = 100; /* wait max 100 ms */ unsigned long timeout = 100; /* wait max 100 ms */
/* reset the controller */ /* reset the controller */
esdhc_write32(&regs->sysctl, SYSCTL_RSTA); esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
/* hardware clears the bit when it is done */ /* hardware clears the bit when it is done */
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)