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arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe 

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Bharat Kumar Gogada 2017-01-30 12:06:02 +05:30 committed by Michal Simek
parent d801ce553e
commit f811eca9db
1 changed files with 2 additions and 2 deletions
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4
arch/arm/dts/zynqmp-zcu102-revA.dts
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@ -168,7 +168,7 @@
gtr_sel0 { gtr_sel0 {
gpio-hog; gpio-hog;
gpios = <0 0>; gpios = <0 0>;
output-high; /* PCIE = 0, DP = 1 */ output-low; /* PCIE = 0, DP = 1 */
line-name = "sel0"; line-name = "sel0";
}; };
gtr_sel1 { gtr_sel1 {
@ -551,7 +551,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
}; };
&pcie { &pcie {
/* status = "okay"; */ status = "okay";
}; };
&qspi { &qspi {