arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14
This resyncs the dts files for all of the currently in-tree K3 platforms, along with relevant bindings, with the v5.14 Linux Kernel release. Of note are that the main-navss/mcu-navss nodes were renamed to main_navss / mcu_navss and so the u-boot.dtsi files needed to be updated to match. Tested on j721e_evm and am65x_evm. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
4698bb8c94
commit
fa09b12dc5
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@ -5,6 +5,17 @@
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/phy/phy-cadence.h>
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#include <dt-bindings/phy/phy-ti.h>
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/ {
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serdes_refclk: clock-cmnrefclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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@ -26,6 +37,20 @@
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};
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};
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main_conf: syscon@43000000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x0 0x43000000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x43000000 0x20000>;
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serdes_ln_ctrl: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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@ -50,12 +75,12 @@
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};
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};
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dmss: dmss {
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dmss: bus@48000000 {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-ranges;
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ranges;
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ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
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ti,sci-dev-id = <25>;
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@ -142,7 +167,7 @@
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};
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};
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dmsc: dmsc@44043000 {
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dmsc: system-controller@44043000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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@ -156,7 +181,7 @@
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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@ -197,8 +222,6 @@
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main_uart0: serial@2800000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -210,8 +233,6 @@
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main_uart1: serial@2810000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -223,8 +244,6 @@
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main_uart2: serial@2820000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -236,8 +255,6 @@
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main_uart3: serial@2830000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -249,8 +266,6 @@
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main_uart4: serial@2840000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -262,8 +277,6 @@
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main_uart5: serial@2850000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -275,8 +288,6 @@
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main_uart6: serial@2860000 {
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compatible = "ti,am64-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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@ -381,6 +392,52 @@
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clocks = <&k3_clks 145 0>;
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};
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main_gpio_intr: interrupt-controller@a00000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x00a00000 0x00 0x800>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <3>;
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ti,interrupt-ranges = <0 32 16>;
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};
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main_gpio0: gpio@600000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00600000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <190>, <191>, <192>,
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<193>, <194>, <195>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <87>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 77 0>;
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clock-names = "gpio";
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};
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main_gpio1: gpio@601000 {
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compatible = "ti,am64-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00601000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <180>, <181>, <182>,
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<183>, <184>, <185>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <88>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 78 0>;
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clock-names = "gpio";
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};
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sdhci0: mmc@fa10000 {
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compatible = "ti,am64-sdhci-8bit";
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reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
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@ -451,7 +508,8 @@
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ti,mac-only;
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label = "port1";
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phys = <&phy_gmii_sel 1>;
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mac-address = [00 00 de ad be ef];
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mac-address = [00 00 00 00 00 00];
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ti,syscon-efuse = <&main_conf 0x200>;
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};
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cpsw_port2: port@2 {
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@ -459,7 +517,7 @@
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ti,mac-only;
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label = "port2";
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phys = <&phy_gmii_sel 2>;
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mac-address = [00 01 de ad be ef];
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mac-address = [00 00 00 00 00 00];
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};
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};
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@ -485,30 +543,23 @@
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};
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};
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main_gpio0: gpio@600000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x00600000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
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<77 1 IRQ_TYPE_EDGE_RISING>,
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<77 2 IRQ_TYPE_EDGE_RISING>,
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<77 3 IRQ_TYPE_EDGE_RISING>,
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<77 4 IRQ_TYPE_EDGE_RISING>,
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<77 5 IRQ_TYPE_EDGE_RISING>,
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<77 6 IRQ_TYPE_EDGE_RISING>,
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<77 7 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <69>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 77 0>;
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clock-names = "gpio";
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cpts@39000000 {
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compatible = "ti,j721e-cpts";
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reg = <0x0 0x39000000 0x0 0x400>;
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reg-names = "cpts";
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power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 84 0>;
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clock-names = "cpts";
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assigned-clocks = <&k3_clks 84 0>;
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assigned-clock-parents = <&k3_clks 84 8>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-periodic-outputs = <6>;
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ti,cpts-ext-ts-inputs = <8>;
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};
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usbss0: cdns-usb@f900000{
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compatible = "ti,am64-usb", "ti,j721e-usb";
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compatible = "ti,am64-usb";
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reg = <0x00 0xf900000 0x00 0x100>;
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power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
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@ -537,69 +588,275 @@
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};
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};
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main_gpio1: gpio@601000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x00601000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
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<78 1 IRQ_TYPE_EDGE_RISING>,
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<78 2 IRQ_TYPE_EDGE_RISING>,
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<78 3 IRQ_TYPE_EDGE_RISING>,
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<78 4 IRQ_TYPE_EDGE_RISING>,
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<78 5 IRQ_TYPE_EDGE_RISING>,
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<78 6 IRQ_TYPE_EDGE_RISING>,
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<78 7 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <69>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 78 0>;
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clock-names = "gpio";
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tscadc0: tscadc@28001000 {
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compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
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reg = <0x00 0x28001000 0x00 0x1000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 0 0>;
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assigned-clocks = <&k3_clks 0 0>;
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assigned-clock-parents = <&k3_clks 0 3>;
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assigned-clock-rates = <60000000>;
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clock-names = "adc_tsc_fck";
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adc {
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#io-channel-cells = <1>;
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compatible = "ti,am654-adc", "ti,am3359-adc";
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};
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};
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main_i2c0: i2c@20000000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x0 0x20000000 0x0 0x100>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 102 2>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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fss: bus@fc00000 {
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compatible = "simple-bus";
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reg = <0x00 0x0fc00000 0x00 0x70000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ospi0: spi@fc40000 {
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compatible = "ti,am654-ospi", "cdns,qspi-nor";
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reg = <0x00 0x0fc40000 0x00 0x100>,
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<0x05 0x00000000 0x01 0x00000000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x0>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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clocks = <&k3_clks 75 6>;
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assigned-clocks = <&k3_clks 75 6>;
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assigned-clock-parents = <&k3_clks 75 7>;
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assigned-clock-rates = <166666666>;
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power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
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};
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};
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main_i2c1: i2c@20010000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x0 0x20010000 0x0 0x100>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 103 2>;
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power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
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hwspinlock: spinlock@2a000000 {
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compatible = "ti,am64-hwspinlock";
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reg = <0x00 0x2a000000 0x00 0x1000>;
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#hwlock-cells = <1>;
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};
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main_i2c2: i2c@20020000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20020000 0x0 0x100>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 104 2>;
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power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
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mailbox0_cluster2: mailbox@29020000 {
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compatible = "ti,am64-mailbox";
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reg = <0x00 0x29020000 0x00 0x200>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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};
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main_i2c3: i2c@20030000 {
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compatible = "ti,am64-i2c", "ti,omap4-i2c";
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reg = <0x00 0x20030000 0x0 0x100>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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mailbox0_cluster3: mailbox@29030000 {
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compatible = "ti,am64-mailbox";
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reg = <0x00 0x29030000 0x00 0x200>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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};
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mailbox0_cluster4: mailbox@29040000 {
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compatible = "ti,am64-mailbox";
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reg = <0x00 0x29040000 0x00 0x200>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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};
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mailbox0_cluster5: mailbox@29050000 {
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compatible = "ti,am64-mailbox";
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reg = <0x00 0x29050000 0x00 0x200>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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};
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mailbox0_cluster6: mailbox@29060000 {
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compatible = "ti,am64-mailbox";
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reg = <0x00 0x29060000 0x00 0x200>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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};
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|
||||
mailbox0_cluster7: mailbox@29070000 {
|
||||
compatible = "ti,am64-mailbox";
|
||||
reg = <0x00 0x29070000 0x00 0x200>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
};
|
||||
|
||||
main_r5fss0: r5fss@78000000 {
|
||||
compatible = "ti,am64-r5fss";
|
||||
ti,cluster-mode = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x78000000 0x00 0x78000000 0x10000>,
|
||||
<0x78100000 0x00 0x78100000 0x10000>,
|
||||
<0x78200000 0x00 0x78200000 0x08000>,
|
||||
<0x78300000 0x00 0x78300000 0x08000>;
|
||||
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
main_r5fss0_core0: r5f@78000000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
reg = <0x78000000 0x00010000>,
|
||||
<0x78100000 0x00010000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <121>;
|
||||
ti,sci-proc-ids = <0x01 0xff>;
|
||||
resets = <&k3_reset 121 1>;
|
||||
firmware-name = "am64-main-r5f0_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
main_r5fss0_core1: r5f@78200000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
reg = <0x78200000 0x00008000>,
|
||||
<0x78300000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <122>;
|
||||
ti,sci-proc-ids = <0x02 0xff>;
|
||||
resets = <&k3_reset 122 1>;
|
||||
firmware-name = "am64-main-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
main_r5fss1: r5fss@78400000 {
|
||||
compatible = "ti,am64-r5fss";
|
||||
ti,cluster-mode = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x78400000 0x00 0x78400000 0x10000>,
|
||||
<0x78500000 0x00 0x78500000 0x10000>,
|
||||
<0x78600000 0x00 0x78600000 0x08000>,
|
||||
<0x78700000 0x00 0x78700000 0x08000>;
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
main_r5fss1_core0: r5f@78400000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
reg = <0x78400000 0x00010000>,
|
||||
<0x78500000 0x00010000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <123>;
|
||||
ti,sci-proc-ids = <0x06 0xff>;
|
||||
resets = <&k3_reset 123 1>;
|
||||
firmware-name = "am64-main-r5f1_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
main_r5fss1_core1: r5f@78600000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
reg = <0x78600000 0x00008000>,
|
||||
<0x78700000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <124>;
|
||||
ti,sci-proc-ids = <0x07 0xff>;
|
||||
resets = <&k3_reset 124 1>;
|
||||
firmware-name = "am64-main-r5f1_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
serdes_wiz0: wiz@f000000 {
|
||||
compatible = "ti,am64-wiz-10g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
num-lanes = <1>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
|
||||
|
||||
assigned-clocks = <&k3_clks 162 1>;
|
||||
assigned-clock-parents = <&k3_clks 162 5>;
|
||||
|
||||
serdes0: serdes@f000000 {
|
||||
compatible = "ti,j721e-serdes-10g";
|
||||
reg = <0x0f000000 0x00010000>;
|
||||
reg-names = "torrent_phy";
|
||||
resets = <&serdes_wiz0 0>;
|
||||
reset-names = "torrent_reset";
|
||||
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
|
||||
clock-names = "refclk", "phy_en_refclk";
|
||||
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
|
||||
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
|
||||
assigned-clock-parents = <&k3_clks 162 1>,
|
||||
<&k3_clks 162 1>,
|
||||
<&k3_clks 162 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_rc: pcie@f102000 {
|
||||
compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x0f102000 0x00 0x1000>,
|
||||
<0x00 0x0f100000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x68000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
|
||||
max-link-speed = <2>;
|
||||
num-lanes = <1>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
|
||||
clock-names = "fck", "pcie_refclk";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
cdns,no-bar-match-nbits = <64>;
|
||||
vendor-id = <0x104c>;
|
||||
device-id = <0xb010>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
|
||||
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@f102000 {
|
||||
compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x0f102000 0x00 0x1000>,
|
||||
<0x00 0x0f100000 0x00 0x400>,
|
||||
<0x00 0x0d000000 0x00 0x00800000>,
|
||||
<0x00 0x68000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
|
||||
max-link-speed = <2>;
|
||||
num-lanes = <1>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "fck";
|
||||
clocks = <&k3_clks 105 2>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
max-functions = /bits/ 8 <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,8 +9,6 @@
|
|||
mcu_uart0: serial@4a00000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -22,8 +20,6 @@
|
|||
mcu_uart1: serial@4a10000 {
|
||||
compatible = "ti,am64-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x04a10000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -73,4 +69,32 @@
|
|||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 148 0>;
|
||||
};
|
||||
|
||||
mcu_gpio_intr: interrupt-controller@4210000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x04210000 0x00 0x200>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
#interrupt-cells = <1>;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <5>;
|
||||
ti,interrupt-ranges = <0 104 4>;
|
||||
};
|
||||
|
||||
mcu_gpio0: gpio@4201000 {
|
||||
compatible = "ti,am64-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x4201000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&mcu_gpio_intr>;
|
||||
interrupts = <30>, <31>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <23>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 79 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,8 +28,6 @@
|
|||
serial6 = &main_uart4;
|
||||
serial7 = &main_uart5;
|
||||
serial8 = &main_uart6;
|
||||
i2c0 = &main_i2c0;
|
||||
i2c1 = &main_i2c1;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
|
|
@ -36,6 +38,60 @@
|
|||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
|
|
@ -154,6 +210,15 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_spi0_pins_default: main-spi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
|
||||
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
|
||||
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
|
||||
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
|
|
@ -207,6 +272,22 @@
|
|||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
|
|
@ -285,6 +366,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* mcu_gpio0 is reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -301,28 +387,16 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
&main_spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
eeprom@0 {
|
||||
compatible = "microchip,93lc46b";
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cs-high;
|
||||
data-size = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -355,3 +429,148 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb0_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
&rgmii1_pins_default
|
||||
&rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy3>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
/* ADC is reserved for R5 usage */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am642.dtsi"
|
||||
|
|
@ -35,6 +37,93 @@
|
|||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: fixed-regulator-vusb-main5v0 {
|
||||
/* USB MAIN INPUT 5V DC */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vusb_main5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
|
||||
/* output of LP8733xx */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vusb_main>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixed-regulator-sd {
|
||||
/* TPS2051BD */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -52,6 +141,12 @@
|
|||
>;
|
||||
};
|
||||
|
||||
main_usb0_pins_default: main-usb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c1_pins_default: main-i2c1-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
|
||||
|
|
@ -99,6 +194,30 @@
|
|||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
|
||||
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
|
||||
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
|
||||
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
|
||||
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
|
||||
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
|
||||
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
|
||||
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
|
||||
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
|
||||
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
|
||||
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
|
|
@ -126,8 +245,51 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp1: gpio@70 {
|
||||
compatible = "nxp,pca9538";
|
||||
reg = <0x70>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"PRU_DETECT", "MMC1_SD_EN",
|
||||
"VPP_LDO_EN", "RPI_PS_3V3_En",
|
||||
"RPI_PS_5V0_En", "RPI_HAT_DETECT";
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_spi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* mcu_gpio0 is reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD/MMC */
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
|
|
@ -135,6 +297,33 @@
|
|||
disable-wp;
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_USB>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_usb_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz0 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "host";
|
||||
maximum-speed = "super-speed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb0_pins_default>;
|
||||
phys = <&serdes0_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio1_pins_default
|
||||
|
|
@ -147,10 +336,120 @@
|
|||
phy-handle = <&cpsw3g_phy0>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
};
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster7 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&pcie0_rc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0_ep {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -84,8 +84,6 @@
|
|||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -95,8 +93,6 @@
|
|||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -105,8 +101,6 @@
|
|||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -256,7 +250,7 @@
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
sdhci0: sdhci@4f80000 {
|
||||
sdhci0: mmc@4f80000 {
|
||||
compatible = "ti,am654-sdhci-5.1";
|
||||
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
|
||||
power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -271,21 +265,16 @@
|
|||
ti,otap-del-sel-sdr12 = <0x0>;
|
||||
ti,otap-del-sel-sdr25 = <0x0>;
|
||||
ti,otap-del-sel-sdr50 = <0x8>;
|
||||
ti,otap-del-sel-sdr104 = <0x5>;
|
||||
ti,otap-del-sel-sdr104 = <0x7>;
|
||||
ti,otap-del-sel-ddr50 = <0x5>;
|
||||
ti,otap-del-sel-ddr52 = <0x5>;
|
||||
ti,otap-del-sel-hs200 = <0x5>;
|
||||
ti,otap-del-sel-hs400 = <0x0>;
|
||||
ti,itap-del-sel-legacy = <0xa>;
|
||||
ti,itap-del-sel-mmc-hs = <0x1>;
|
||||
ti,itap-del-sel-sdr12 = <0xa>;
|
||||
ti,itap-del-sel-sdr25 = <0x1>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,trm-icp = <0x8>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
sdhci1: sdhci@4fa0000 {
|
||||
sdhci1: mmc@4fa0000 {
|
||||
compatible = "ti,am654-sdhci-5.1";
|
||||
reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
|
||||
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -302,11 +291,8 @@
|
|||
ti,otap-del-sel-ddr50 = <0x4>;
|
||||
ti,otap-del-sel-ddr52 = <0x4>;
|
||||
ti,otap-del-sel-hs200 = <0x7>;
|
||||
ti,itap-del-sel-legacy = <0xa>;
|
||||
ti,itap-del-sel-mmc-hs = <0x1>;
|
||||
ti,itap-del-sel-sdr12 = <0xa>;
|
||||
ti,itap-del-sel-sdr25 = <0x1>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,otap-del-sel = <0x2>;
|
||||
ti,trm-icp = <0x8>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
|
@ -440,8 +426,9 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
intr_main_gpio: interrupt-controller0 {
|
||||
intr_main_gpio: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x0 0x00a00000 0x0 0x400>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -451,18 +438,19 @@
|
|||
ti,interrupt-ranges = <0 392 32>;
|
||||
};
|
||||
|
||||
main-navss {
|
||||
main_navss: bus@30800000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <118>;
|
||||
|
||||
intr_main_navss: interrupt-controller1 {
|
||||
intr_main_navss: interrupt-controller@310e0000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x0 0x310e0000 0x0 0x2000>;
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -714,6 +702,7 @@
|
|||
dma-coherent;
|
||||
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pcie0_ep: pcie-ep@5500000 {
|
||||
|
|
@ -746,6 +735,7 @@
|
|||
dma-coherent;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-map = <0x0 &gic_its 0x10000 0x10000>;
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@5600000 {
|
||||
|
|
@ -974,18 +964,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
icssg0_iep0: iep@2e000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2e000 0x1000>;
|
||||
clocks = <&icssg0_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg0_iep1: iep@2f000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2f000 0x1000>;
|
||||
clocks = <&icssg0_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg0_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
|
|
@ -1077,7 +1055,6 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1128,18 +1105,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
icssg1_iep0: iep@2e000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2e000 0x1000>;
|
||||
clocks = <&icssg1_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg1_iep1: iep@2f000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2f000 0x1000>;
|
||||
clocks = <&icssg1_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg1_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
|
|
@ -1231,7 +1196,6 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1282,18 +1246,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
icssg2_iep0: iep@2e000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2e000 0x1000>;
|
||||
clocks = <&icssg2_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg2_iep1: iep@2f000 {
|
||||
compatible = "ti,am654-icss-iep";
|
||||
reg = <0x2f000 0x1000>;
|
||||
clocks = <&icssg2_iepclk_mux>;
|
||||
};
|
||||
|
||||
icssg2_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
|
|
@ -1385,8 +1337,6 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,8 +23,6 @@
|
|||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -116,11 +114,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
mcu-navss {
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
|
|
@ -308,4 +306,13 @@
|
|||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
mcu_rti1: watchdog@40610000 {
|
||||
compatible = "ti,j7-rti-wdt";
|
||||
reg = <0x0 0x40610000 0x0 0x100>;
|
||||
clocks = <&k3_clks 135 0>;
|
||||
power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
|
||||
assigned-clocks = <&k3_clks 135 0>;
|
||||
assigned-clock-parents = <&k3_clks 135 4>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,24 +6,24 @@
|
|||
*/
|
||||
|
||||
&cbass_wakeup {
|
||||
dmsc: dmsc {
|
||||
dmsc: system-controller@44083000 {
|
||||
compatible = "ti,am654-sci";
|
||||
ti,host-id = <12>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mbox-names = "rx", "tx";
|
||||
|
||||
mboxes= <&secure_proxy_main 11>,
|
||||
<&secure_proxy_main 13>;
|
||||
|
||||
reg-names = "debug_messages";
|
||||
reg = <0x44083000 0x1000>;
|
||||
|
||||
k3_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
@ -50,8 +50,6 @@
|
|||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,am654-uart";
|
||||
reg = <0x42300000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -69,8 +67,9 @@
|
|||
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
intr_wkup_gpio: interrupt-controller2 {
|
||||
intr_wkup_gpio: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x42200000 0x200>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -86,10 +86,36 @@
|
|||
};
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_io: fixedregulator-vcc3v3io {
|
||||
/* Output of TPS54334 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&evm_12v0>;
|
||||
};
|
||||
|
||||
vdd_mmc1_sd: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc3v3_io>;
|
||||
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -142,7 +168,7 @@
|
|||
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
|
||||
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
|
||||
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
|
||||
AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
|
||||
AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
|
||||
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
|
@ -287,23 +313,6 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2_phy0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
|
|
@ -322,7 +331,7 @@
|
|||
pinctrl-0 = <&main_spi0_pins_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells= <0>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
@ -350,10 +359,10 @@
|
|||
* disable sdhci1
|
||||
*/
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vdd_mmc1_sd>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc1_pins_default>;
|
||||
ti,driver-strength-ohm = <50>;
|
||||
sdhci-caps-mask = <0x7 0x0>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
|
|
@ -484,9 +493,9 @@
|
|||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
|
|
@ -497,14 +506,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&csi2_0 {
|
||||
csi2_phy0: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
|
|
@ -538,3 +539,15 @@
|
|||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg2_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
main-navss {
|
||||
main_navss: bus@30800000 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
&cbass_mcu {
|
||||
u-boot,dm-spl;
|
||||
|
||||
mcu-navss {
|
||||
mcu_navss: bus@28380000 {
|
||||
u-boot,dm-spl;
|
||||
|
||||
ringacc@2b800000 {
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
mcu-navss{
|
||||
mcu_navss: bus@28380000 {
|
||||
u-boot,dm-spl;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -118,10 +118,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_i2c0_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_i2c0 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
@ -165,10 +161,6 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&wkup_gpio_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
&mcu_fss0_hpb0_pins_default {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,51 +17,67 @@
|
|||
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
|
||||
};
|
||||
|
||||
aliases {
|
||||
remoteproc0 = &mcu_r5fss0_core0;
|
||||
remoteproc1 = &mcu_r5fss0_core1;
|
||||
remoteproc2 = &main_r5fss0_core0;
|
||||
remoteproc3 = &main_r5fss0_core1;
|
||||
evm_12v0: fixedregulator-evm12v0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_3v3: fixedregulator-vsys3v3 {
|
||||
/* Output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_5v0: fixedregulator-vsys5v0 {
|
||||
/* Output of LM5140 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&evm_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: fixedregulator-sd {
|
||||
/* Output of TPS22918 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vsys_3v3>;
|
||||
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: gpio-regulator-vdd-sd-dv {
|
||||
vdd_sd_dv: gpio-regulator-TLV71033 {
|
||||
/* Output of TLV71033 */
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vdd_sd_dv";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vsys_5v0>;
|
||||
gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0
|
||||
3300000 0x1>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
|
||||
J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
wkup_gpio_pins_default: wkup-gpio-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
|
||||
|
|
@ -74,7 +90,7 @@
|
|||
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
|
||||
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
|
||||
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
|
||||
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
|
@ -115,17 +131,17 @@
|
|||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usbss0_pins_default: main-usbss0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
|
|
@ -178,6 +194,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&main_gpio6 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_gpio1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||||
|
|
@ -288,7 +320,7 @@
|
|||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_link: link@0 {
|
||||
serdes0_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -296,7 +328,7 @@
|
|||
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
|
||||
};
|
||||
|
||||
serdes0_qsgmii_link: link@1 {
|
||||
serdes0_qsgmii_link: phy@1 {
|
||||
reg = <2>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -304,3 +336,17 @@
|
|||
resets = <&serdes_wiz0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie1_rc {
|
||||
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for J7200 SoC Family Main Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/ {
|
||||
|
|
@ -68,8 +68,9 @@
|
|||
};
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -85,9 +86,12 @@
|
|||
#size-cells = <2>;
|
||||
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
|
||||
ti,sci-dev-id = <199>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
main_navss_intr: interrupt-controller1 {
|
||||
main_navss_intr: interrupt-controller@310e0000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x310e0000 0x00 0x4000>;
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -297,8 +301,6 @@
|
|||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -310,8 +312,6 @@
|
|||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -323,8 +323,6 @@
|
|||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -336,8 +334,6 @@
|
|||
main_uart3: serial@2830000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02830000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -349,8 +345,6 @@
|
|||
main_uart4: serial@2840000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02840000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -362,8 +356,6 @@
|
|||
main_uart5: serial@2850000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02850000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -375,8 +367,6 @@
|
|||
main_uart6: serial@2860000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02860000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -388,8 +378,6 @@
|
|||
main_uart7: serial@2870000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02870000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -401,8 +389,6 @@
|
|||
main_uart8: serial@2880000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02880000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -414,8 +400,6 @@
|
|||
main_uart9: serial@2890000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02890000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -424,53 +408,6 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
main_sdhci0: sdhci@4f80000 {
|
||||
compatible = "ti,j721e-sdhci-8bit";
|
||||
reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x6>;
|
||||
ti,otap-del-sel-hs200 = <0x8>;
|
||||
ti,otap-del-sel-hs400 = <0x5>;
|
||||
ti,itap-del-sel-legacy = <0x10>;
|
||||
ti,itap-del-sel-mmc-hs = <0xa>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,trm-icp = <0x8>;
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
main_sdhci1: sdhci@4fb0000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x5>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,trm-icp = <0x8>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
main_i2c0: i2c@2000000 {
|
||||
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
||||
reg = <0x00 0x2000000 0x00 0x100>;
|
||||
|
|
@ -548,26 +485,51 @@
|
|||
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x0 0x00600000 0x0 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 1 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 2 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 3 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 4 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 5 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 6 IRQ_TYPE_EDGE_RISING>,
|
||||
<105 7 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 0>;
|
||||
clock-names = "gpio";
|
||||
main_sdhci0: mmc@4f80000 {
|
||||
compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
|
||||
reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-mmc-hs = <0x0>;
|
||||
ti,otap-del-sel-ddr52 = <0x6>;
|
||||
ti,otap-del-sel-hs200 = <0x8>;
|
||||
ti,otap-del-sel-hs400 = <0x5>;
|
||||
ti,itap-del-sel-legacy = <0x10>;
|
||||
ti,itap-del-sel-mmc-hs = <0xa>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,trm-icp = <0x8>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
main_sdhci1: mmc@4fb0000 {
|
||||
compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
|
||||
reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
ti,otap-del-sel-sdr104 = <0x5>;
|
||||
ti,otap-del-sel-ddr50 = <0xc>;
|
||||
ti,itap-del-sel-legacy = <0x0>;
|
||||
ti,itap-del-sel-sd-hs = <0x0>;
|
||||
ti,itap-del-sel-sdr12 = <0x0>;
|
||||
ti,itap-del-sel-sdr25 = <0x0>;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,trm-icp = <0x8>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
serdes_wiz0: wiz@5060000 {
|
||||
|
|
@ -626,6 +588,54 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie1_rc: pcie@2910000 {
|
||||
compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
|
||||
reg = <0x00 0x02910000 0x00 0x1000>,
|
||||
<0x00 0x02917000 0x00 0x400>,
|
||||
<0x00 0x0d800000 0x00 0x00800000>,
|
||||
<0x00 0x18000000 0x00 0x00001000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <4>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 240 6>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x0 0xf>;
|
||||
cdns,no-bar-match-nbits = <64>;
|
||||
vendor-id = /bits/ 16 <0x104c>;
|
||||
device-id = /bits/ 16 <0xb00f>;
|
||||
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
||||
dma-coherent;
|
||||
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
|
||||
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
|
||||
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
|
||||
};
|
||||
|
||||
pcie1_ep: pcie-ep@2910000 {
|
||||
compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
|
||||
reg = <0x00 0x02910000 0x00 0x1000>,
|
||||
<0x00 0x02917000 0x00 0x400>,
|
||||
<0x00 0x0d800000 0x00 0x00800000>,
|
||||
<0x00 0x18000000 0x00 0x08000000>;
|
||||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <4>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 240 6>;
|
||||
clock-names = "fck";
|
||||
max-functions = /bits/ 8 <6>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
usbss0: cdns-usb@4104000 {
|
||||
compatible = "ti,j721e-usb";
|
||||
reg = <0x00 0x4104000 0x00 0x100>;
|
||||
|
|
@ -653,12 +663,81 @@
|
|||
"otg";
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
cdns,phyrst-a-enable;
|
||||
};
|
||||
};
|
||||
|
||||
main_gpio0: gpio@600000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00600000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <145>, <146>, <147>, <148>,
|
||||
<149>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 105 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio2: gpio@610000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00610000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <154>, <155>, <156>, <157>,
|
||||
<158>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 107 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio4: gpio@620000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00620000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <163>, <164>, <165>, <166>,
|
||||
<167>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 109 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_gpio6: gpio@630000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x00630000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&main_gpio_intr>;
|
||||
interrupts = <172>, <173>, <174>, <175>,
|
||||
<176>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <69>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 111 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_r5fss0: r5fss@5c00000 {
|
||||
compatible = "ti,j7200-r5fss";
|
||||
ti,cluster-mode = <0>;
|
||||
ti,cluster-mode = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
|
||||
|
|
@ -672,7 +751,7 @@
|
|||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <245>;
|
||||
ti,sci-proc-ids = <0x06 0xFF>;
|
||||
ti,sci-proc-ids = <0x06 0xff>;
|
||||
resets = <&k3_reset 245 1>;
|
||||
firmware-name = "j7200-main-r5f0_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
|
|
@ -687,7 +766,7 @@
|
|||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <246>;
|
||||
ti,sci-proc-ids = <0x07 0xFF>;
|
||||
ti,sci-proc-ids = <0x07 0xff>;
|
||||
resets = <&k3_reset 246 1>;
|
||||
firmware-name = "j7200-main-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
|
|
|
|||
|
|
@ -2,11 +2,11 @@
|
|||
/*
|
||||
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
dmsc: dmsc@44083000 {
|
||||
dmsc: system-controller@44083000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
@ -73,8 +73,6 @@
|
|||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x42300000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -86,8 +84,6 @@
|
|||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -96,8 +92,9 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_gpio_intr: interrupt-controller2 {
|
||||
wkup_gpio_intr: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x42200000 0x00 0x400>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -107,6 +104,38 @@
|
|||
ti,interrupt-ranges = <16 960 16>;
|
||||
};
|
||||
|
||||
wkup_gpio0: gpio@42110000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x42110000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <85>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 113 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
wkup_gpio1: gpio@42100000 {
|
||||
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
||||
reg = <0x00 0x42100000 0x00 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&wkup_gpio_intr>;
|
||||
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,ngpio = <85>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 114 0>;
|
||||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -269,6 +298,23 @@
|
|||
#size-cells = <1>;
|
||||
mux-controls = <&hbmc_mux 0>;
|
||||
};
|
||||
|
||||
ospi0: spi@47040000 {
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x0 0x47040000 0x0 0x100>,
|
||||
<0x5 0x00000000 0x1 0x0000000>;
|
||||
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
clocks = <&k3_clks 103 0>;
|
||||
assigned-clocks = <&k3_clks 103 0>;
|
||||
assigned-clock-parents = <&k3_clks 103 2>;
|
||||
assigned-clock-rates = <166666666>;
|
||||
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tscadc0: tscadc@40200000 {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -25,6 +25,60 @@
|
|||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a4000000 {
|
||||
reg = <0x00 0xa4000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -46,6 +100,22 @@
|
|||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
|
||||
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
|
||||
J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */
|
||||
J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */
|
||||
J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */
|
||||
J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */
|
||||
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */
|
||||
J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */
|
||||
J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
|
||||
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
|
||||
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
|
|
@ -141,6 +211,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
|
@ -157,3 +251,23 @@
|
|||
"GPIO_LIN_EN", "CAN_STB";
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@
|
|||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
&cbass_main{
|
||||
u-boot,dm-spl;
|
||||
|
||||
main-navss {
|
||||
main_navss: bus@30000000 {
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
|
@ -50,7 +50,7 @@
|
|||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
mcu-navss {
|
||||
mcu_navss: bus@28380000 {
|
||||
u-boot,dm-spl;
|
||||
|
||||
ringacc@2b800000 {
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/phy/phy-cadence.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
|
|
@ -237,7 +238,7 @@
|
|||
J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
|
||||
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
|
||||
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
|
||||
J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
|
||||
J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
|
||||
>;
|
||||
};
|
||||
|
|
@ -358,7 +359,7 @@
|
|||
};
|
||||
|
||||
&serdes3 {
|
||||
serdes3_usb_link: link@0 {
|
||||
serdes3_usb_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -635,8 +636,45 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&cmn_refclk1 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&wiz0_pll1_refclk {
|
||||
assigned-clocks = <&wiz0_pll1_refclk>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz0_refclk_dig {
|
||||
assigned-clocks = <&wiz0_refclk_dig>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz1_pll1_refclk {
|
||||
assigned-clocks = <&wiz1_pll1_refclk>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz1_refclk_dig {
|
||||
assigned-clocks = <&wiz1_refclk_dig>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz2_pll1_refclk {
|
||||
assigned-clocks = <&wiz2_pll1_refclk>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&wiz2_refclk_dig {
|
||||
assigned-clocks = <&wiz2_refclk_dig>;
|
||||
assigned-clock-parents = <&cmn_refclk1>;
|
||||
};
|
||||
|
||||
&serdes0 {
|
||||
serdes0_pcie_link: link@0 {
|
||||
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
|
||||
assigned-clock-parents = <&wiz0_pll1_refclk>;
|
||||
|
||||
serdes0_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -646,7 +684,10 @@
|
|||
};
|
||||
|
||||
&serdes1 {
|
||||
serdes1_pcie_link: link@0 {
|
||||
assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
|
||||
assigned-clock-parents = <&wiz1_pll1_refclk>;
|
||||
|
||||
serdes1_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -656,7 +697,10 @@
|
|||
};
|
||||
|
||||
&serdes2 {
|
||||
serdes2_pcie_link: link@0 {
|
||||
assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
|
||||
assigned-clock-parents = <&wiz2_pll1_refclk>;
|
||||
|
||||
serdes2_pcie_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -718,3 +762,11 @@
|
|||
&dss {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg0_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,20 @@
|
|||
#include <dt-bindings/mux/mux.h>
|
||||
#include <dt-bindings/mux/ti-serdes.h>
|
||||
|
||||
/ {
|
||||
cmn_refclk: clock-cmnrefclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cmn_refclk1: clock-cmnrefclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
msmc_ram: sram@70000000 {
|
||||
compatible = "mmio-sram";
|
||||
|
|
@ -28,38 +42,6 @@
|
|||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x00100000 0x1c000>;
|
||||
|
||||
pcie0_ctrl: syscon@4070 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004070 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4070 0x4070 0x4>;
|
||||
};
|
||||
|
||||
pcie1_ctrl: syscon@4074 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004074 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4074 0x4074 0x4>;
|
||||
};
|
||||
|
||||
pcie2_ctrl: syscon@4078 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004078 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4078 0x4078 0x4>;
|
||||
};
|
||||
|
||||
pcie3_ctrl: syscon@407c {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x0000407c 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x407c 0x407c 0x4>;
|
||||
};
|
||||
|
||||
serdes_ln_ctrl: mux@4080 {
|
||||
compatible = "mmio-mux";
|
||||
reg = <0x00004080 0x50>;
|
||||
|
|
@ -108,8 +90,9 @@
|
|||
};
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -119,18 +102,19 @@
|
|||
ti,interrupt-ranges = <8 392 56>;
|
||||
};
|
||||
|
||||
main-navss {
|
||||
main_navss: bus@30000000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
ti,sci-dev-id = <199>;
|
||||
|
||||
main_navss_intr: interrupt-controller1 {
|
||||
main_navss_intr: interrupt-controller@310e0000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x0 0x310e0000 0x0 0x4000>;
|
||||
ti,intr-trigger-type = <4>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -368,24 +352,12 @@
|
|||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
dummy_cmn_refclk: dummy-cmn-refclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
dummy_cmn_refclk1: dummy-cmn-refclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
serdes_wiz0: wiz@5000000 {
|
||||
compatible = "ti,j721e-wiz-16g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
|
||||
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
|
||||
|
|
@ -394,21 +366,21 @@
|
|||
ranges = <0x5000000 0x0 0x5000000 0x10000>;
|
||||
|
||||
wiz0_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 292 11>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 292 11>;
|
||||
};
|
||||
|
||||
wiz0_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 292 0>;
|
||||
};
|
||||
|
||||
wiz0_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 292 11>;
|
||||
|
|
@ -430,10 +402,13 @@
|
|||
reg = <0x5000000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz0 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
|
||||
<&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -442,7 +417,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
|
||||
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
|
||||
|
|
@ -451,21 +426,21 @@
|
|||
ranges = <0x5010000 0x0 0x5010000 0x10000>;
|
||||
|
||||
wiz1_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 293 13>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 293 13>;
|
||||
};
|
||||
|
||||
wiz1_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 293 0>;
|
||||
};
|
||||
|
||||
wiz1_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 293 13>;
|
||||
|
|
@ -487,10 +462,13 @@
|
|||
reg = <0x5010000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz1 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
|
||||
<&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -499,7 +477,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
|
||||
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
|
||||
|
|
@ -508,21 +486,21 @@
|
|||
ranges = <0x5020000 0x0 0x5020000 0x10000>;
|
||||
|
||||
wiz2_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 294 11>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 294 11>;
|
||||
};
|
||||
|
||||
wiz2_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 294 0>;
|
||||
};
|
||||
|
||||
wiz2_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 294 11>;
|
||||
|
|
@ -544,10 +522,13 @@
|
|||
reg = <0x5020000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz2 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
|
||||
<&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -556,7 +537,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
|
||||
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
|
||||
|
|
@ -565,21 +546,21 @@
|
|||
ranges = <0x5030000 0x0 0x5030000 0x10000>;
|
||||
|
||||
wiz3_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
|
||||
clocks = <&k3_clks 295 9>, <&cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 295 9>;
|
||||
};
|
||||
|
||||
wiz3_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 295 0>;
|
||||
};
|
||||
|
||||
wiz3_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 295 9>;
|
||||
|
|
@ -601,10 +582,13 @@
|
|||
reg = <0x5030000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
resets = <&serdes_wiz3 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
|
||||
<&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
|
||||
"pll0_refclk", "pll1_refclk";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -618,7 +602,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -645,13 +629,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 239 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -667,7 +650,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -694,13 +677,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 240 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -716,7 +698,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -743,13 +725,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 241 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -765,7 +746,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -792,13 +773,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 242 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -809,8 +789,6 @@
|
|||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -822,8 +800,6 @@
|
|||
main_uart1: serial@2810000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02810000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -835,8 +811,6 @@
|
|||
main_uart2: serial@2820000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02820000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -848,8 +822,6 @@
|
|||
main_uart3: serial@2830000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02830000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -861,8 +833,6 @@
|
|||
main_uart4: serial@2840000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02840000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -874,8 +844,6 @@
|
|||
main_uart5: serial@2850000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02850000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -887,8 +855,6 @@
|
|||
main_uart6: serial@2860000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02860000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -900,8 +866,6 @@
|
|||
main_uart7: serial@2870000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02870000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -913,8 +877,6 @@
|
|||
main_uart8: serial@2880000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02880000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -926,8 +888,6 @@
|
|||
main_uart9: serial@2890000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02890000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -1068,13 +1028,13 @@
|
|||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_sdhci0: sdhci@4f80000 {
|
||||
main_sdhci0: mmc@4f80000 {
|
||||
compatible = "ti,j721e-sdhci-8bit";
|
||||
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
|
||||
assigned-clocks = <&k3_clks 91 1>;
|
||||
assigned-clock-parents = <&k3_clks 91 2>;
|
||||
bus-width = <8>;
|
||||
|
|
@ -1084,24 +1044,26 @@
|
|||
ti,otap-del-sel-mmc-hs = <0xf>;
|
||||
ti,otap-del-sel-ddr52 = <0x5>;
|
||||
ti,otap-del-sel-hs200 = <0x6>;
|
||||
ti,otap-del-sel-hs400 = <0x0>;
|
||||
ti,itap-del-sel-legacy = <0x10>;
|
||||
ti,itap-del-sel-mmc-hs = <0xa>;
|
||||
ti,itap-del-sel-ddr52 = <0x3>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
main_sdhci1: sdhci@4fb0000 {
|
||||
main_sdhci1: mmc@4fb0000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
|
||||
assigned-clocks = <&k3_clks 92 0>;
|
||||
assigned-clock-parents = <&k3_clks 92 1>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0xf>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
|
|
@ -1117,17 +1079,17 @@
|
|||
sdhci-caps-mask = <0x2 0x0>;
|
||||
};
|
||||
|
||||
main_sdhci2: sdhci@4f98000 {
|
||||
main_sdhci2: mmc@4f98000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
|
||||
assigned-clocks = <&k3_clks 93 0>;
|
||||
assigned-clock-parents = <&k3_clks 93 1>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0x0>;
|
||||
ti,otap-del-sel-sd-hs = <0xf>;
|
||||
ti,otap-del-sel-sdr12 = <0xf>;
|
||||
ti,otap-del-sel-sdr25 = <0xf>;
|
||||
ti,otap-del-sel-sdr50 = <0xc>;
|
||||
|
|
@ -1696,4 +1658,286 @@
|
|||
resets = <&k3_reset 15 1>;
|
||||
firmware-name = "j7-c71_0-fw";
|
||||
};
|
||||
|
||||
icssg0: icssg@b000000 {
|
||||
compatible = "ti,j721e-icssg";
|
||||
reg = <0x00 0xb000000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x0b000000 0x100000>;
|
||||
|
||||
icssg0_mem: memories@0 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1",
|
||||
"shrdram2";
|
||||
};
|
||||
|
||||
icssg0_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg0_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
|
||||
<&k3_clks 119 1>; /* icssg0_iclk */
|
||||
assigned-clocks = <&icssg0_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 119 1>;
|
||||
};
|
||||
|
||||
icssg0_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
|
||||
<&icssg0_coreclk_mux>; /* core_clk */
|
||||
assigned-clocks = <&icssg0_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg0_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg0_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg0_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg0_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru0_0: pru@34000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x34000 0x3000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru0_0-fw";
|
||||
};
|
||||
|
||||
rtu0_0: rtu@4000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu0_0-fw";
|
||||
};
|
||||
|
||||
tx_pru0_0: txpru@a000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru0_0-fw";
|
||||
};
|
||||
|
||||
pru0_1: pru@38000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x38000 0x3000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru0_1-fw";
|
||||
};
|
||||
|
||||
rtu0_1: rtu@6000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu0_1-fw";
|
||||
};
|
||||
|
||||
tx_pru0_1: txpru@c000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru0_1-fw";
|
||||
};
|
||||
|
||||
icssg0_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 119 1>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
icssg1: icssg@b100000 {
|
||||
compatible = "ti,j721e-icssg";
|
||||
reg = <0x00 0xb100000 0x00 0x80000>;
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x0b100000 0x100000>;
|
||||
|
||||
icssg1_mem: memories@b100000 {
|
||||
reg = <0x0 0x2000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x10000 0x10000>;
|
||||
reg-names = "dram0", "dram1",
|
||||
"shrdram2";
|
||||
};
|
||||
|
||||
icssg1_cfg: cfg@26000 {
|
||||
compatible = "ti,pruss-cfg", "syscon";
|
||||
reg = <0x26000 0x200>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x2000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
icssg1_coreclk_mux: coreclk-mux@3c {
|
||||
reg = <0x3c>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
|
||||
<&k3_clks 120 4>; /* icssg1_iclk */
|
||||
assigned-clocks = <&icssg1_coreclk_mux>;
|
||||
assigned-clock-parents = <&k3_clks 120 4>;
|
||||
};
|
||||
|
||||
icssg1_iepclk_mux: iepclk-mux@30 {
|
||||
reg = <0x30>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
|
||||
<&icssg1_coreclk_mux>; /* core_clk */
|
||||
assigned-clocks = <&icssg1_iepclk_mux>;
|
||||
assigned-clock-parents = <&icssg1_coreclk_mux>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
icssg1_mii_rt: mii-rt@32000 {
|
||||
compatible = "ti,pruss-mii", "syscon";
|
||||
reg = <0x32000 0x100>;
|
||||
};
|
||||
|
||||
icssg1_mii_g_rt: mii-g-rt@33000 {
|
||||
compatible = "ti,pruss-mii-g", "syscon";
|
||||
reg = <0x33000 0x1000>;
|
||||
};
|
||||
|
||||
icssg1_intc: interrupt-controller@20000 {
|
||||
compatible = "ti,icssg-intc";
|
||||
reg = <0x20000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host_intr0", "host_intr1",
|
||||
"host_intr2", "host_intr3",
|
||||
"host_intr4", "host_intr5",
|
||||
"host_intr6", "host_intr7";
|
||||
};
|
||||
|
||||
pru1_0: pru@34000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x34000 0x4000>,
|
||||
<0x22000 0x100>,
|
||||
<0x22400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru1_0-fw";
|
||||
};
|
||||
|
||||
rtu1_0: rtu@4000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x4000 0x2000>,
|
||||
<0x23000 0x100>,
|
||||
<0x23400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu1_0-fw";
|
||||
};
|
||||
|
||||
tx_pru1_0: txpru@a000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xa000 0x1800>,
|
||||
<0x25000 0x100>,
|
||||
<0x25400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru1_0-fw";
|
||||
};
|
||||
|
||||
pru1_1: pru@38000 {
|
||||
compatible = "ti,j721e-pru";
|
||||
reg = <0x38000 0x4000>,
|
||||
<0x24000 0x100>,
|
||||
<0x24400 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-pru1_1-fw";
|
||||
};
|
||||
|
||||
rtu1_1: rtu@6000 {
|
||||
compatible = "ti,j721e-rtu";
|
||||
reg = <0x6000 0x2000>,
|
||||
<0x23800 0x100>,
|
||||
<0x23c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-rtu1_1-fw";
|
||||
};
|
||||
|
||||
tx_pru1_1: txpru@c000 {
|
||||
compatible = "ti,j721e-tx-pru";
|
||||
reg = <0xc000 0x1800>,
|
||||
<0x25800 0x100>,
|
||||
<0x25c00 0x100>;
|
||||
reg-names = "iram", "control", "debug";
|
||||
firmware-name = "j7-txpru1_1-fw";
|
||||
};
|
||||
|
||||
icssg1_mdio: mdio@32400 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
reg = <0x32400 0x100>;
|
||||
clocks = <&k3_clks 120 4>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
dmsc: dmsc@44083000 {
|
||||
dmsc: system-controller@44083000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
|
||||
|
|
@ -23,7 +23,7 @@
|
|||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
@ -73,8 +73,6 @@
|
|||
wkup_uart0: serial@42300000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x42300000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <48000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -86,8 +84,6 @@
|
|||
mcu_uart0: serial@40a00000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x40a00000 0x00 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <96000000>;
|
||||
current-speed = <115200>;
|
||||
|
|
@ -96,8 +92,9 @@
|
|||
clock-names = "fclk";
|
||||
};
|
||||
|
||||
wkup_gpio_intr: interrupt-controller2 {
|
||||
wkup_gpio_intr: interrupt-controller@42200000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x42200000 0x00 0x400>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -179,26 +176,8 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
hbmc_mux: hbmc-mux {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x4 0x2>; /* HBMC select */
|
||||
};
|
||||
|
||||
hbmc: hyperbus@47034000 {
|
||||
compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
|
||||
reg = <0x0 0x47034000 0x0 0x100>,
|
||||
<0x5 0x00000000 0x1 0x0000000>;
|
||||
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
mux-controls = <&hbmc_mux 0>;
|
||||
assigned-clocks = <&k3_clks 102 0>;
|
||||
assigned-clock-rates = <250000000>;
|
||||
};
|
||||
|
||||
ospi0: spi@47040000 {
|
||||
compatible = "ti,am654-ospi";
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x0 0x47040000 0x0 0x100>,
|
||||
<0x5 0x00000000 0x1 0x0000000>;
|
||||
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -215,7 +194,7 @@
|
|||
};
|
||||
|
||||
ospi1: spi@47050000 {
|
||||
compatible = "ti,am654-ospi";
|
||||
compatible = "ti,am654-ospi", "cdns,qspi-nor";
|
||||
reg = <0x0 0x47050000 0x0 0x100>,
|
||||
<0x7 0x00000000 0x1 0x00000000>;
|
||||
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -267,11 +246,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
mcu-navss {
|
||||
mcu_navss: bus@28380000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
|
|
|
|||
|
|
@ -150,25 +150,6 @@
|
|||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
|
||||
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
|
||||
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
|
||||
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
|
||||
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
|
||||
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
|
||||
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
|
||||
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
|
||||
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
|
||||
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
|
||||
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
|
||||
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
|
||||
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
|
||||
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
|
||||
|
|
@ -186,19 +167,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&hbmc {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
|
||||
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
|
||||
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cypress,hyperflash", "cfi-flash";
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
|
@ -206,9 +174,9 @@
|
|||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@
|
|||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
|
@ -126,7 +126,6 @@
|
|||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
|
||||
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
||||
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* TI DP83867 PHY drivers
|
||||
* Device Tree constants for the Texas Instruments DP83867 PHY
|
||||
*
|
||||
* Author: Dan Murphy <dmurphy@ti.com>
|
||||
*
|
||||
* Copyright: (C) 2015 Texas Instruments, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_TI_DP83867_H
|
||||
|
|
@ -14,22 +17,22 @@
|
|||
#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
|
||||
|
||||
/* RGMIIDCTL internal delay for rx and tx */
|
||||
#define DP83867_RGMIIDCTL_250_PS 0x0
|
||||
#define DP83867_RGMIIDCTL_500_PS 0x1
|
||||
#define DP83867_RGMIIDCTL_750_PS 0x2
|
||||
#define DP83867_RGMIIDCTL_1_NS 0x3
|
||||
#define DP83867_RGMIIDCTL_1_25_NS 0x4
|
||||
#define DP83867_RGMIIDCTL_1_50_NS 0x5
|
||||
#define DP83867_RGMIIDCTL_1_75_NS 0x6
|
||||
#define DP83867_RGMIIDCTL_2_00_NS 0x7
|
||||
#define DP83867_RGMIIDCTL_2_25_NS 0x8
|
||||
#define DP83867_RGMIIDCTL_2_50_NS 0x9
|
||||
#define DP83867_RGMIIDCTL_2_75_NS 0xa
|
||||
#define DP83867_RGMIIDCTL_3_00_NS 0xb
|
||||
#define DP83867_RGMIIDCTL_3_25_NS 0xc
|
||||
#define DP83867_RGMIIDCTL_3_50_NS 0xd
|
||||
#define DP83867_RGMIIDCTL_3_75_NS 0xe
|
||||
#define DP83867_RGMIIDCTL_4_00_NS 0xf
|
||||
#define DP83867_RGMIIDCTL_250_PS 0x0
|
||||
#define DP83867_RGMIIDCTL_500_PS 0x1
|
||||
#define DP83867_RGMIIDCTL_750_PS 0x2
|
||||
#define DP83867_RGMIIDCTL_1_NS 0x3
|
||||
#define DP83867_RGMIIDCTL_1_25_NS 0x4
|
||||
#define DP83867_RGMIIDCTL_1_50_NS 0x5
|
||||
#define DP83867_RGMIIDCTL_1_75_NS 0x6
|
||||
#define DP83867_RGMIIDCTL_2_00_NS 0x7
|
||||
#define DP83867_RGMIIDCTL_2_25_NS 0x8
|
||||
#define DP83867_RGMIIDCTL_2_50_NS 0x9
|
||||
#define DP83867_RGMIIDCTL_2_75_NS 0xa
|
||||
#define DP83867_RGMIIDCTL_3_00_NS 0xb
|
||||
#define DP83867_RGMIIDCTL_3_25_NS 0xc
|
||||
#define DP83867_RGMIIDCTL_3_50_NS 0xd
|
||||
#define DP83867_RGMIIDCTL_3_75_NS 0xe
|
||||
#define DP83867_RGMIIDCTL_4_00_NS 0xf
|
||||
|
||||
/* IO_MUX_CFG - Clock output selection */
|
||||
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
|
||||
|
|
|
|||
Loading…
Reference in New Issue