ppc: Remove MPC8349EMDS board and ARCH_MPC8349 support
This board has not been converted to CONFIG_DM by the deadline. Remove it. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
4987658be5
commit
fae2ea5951
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@ -8,22 +8,6 @@ choice
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prompt "Target select"
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prompt "Target select"
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optional
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optional
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config TARGET_MPC8349EMDS
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bool "Support MPC8349EMDS"
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select ARCH_MPC8349
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select BOARD_EARLY_INIT_F
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_HAS_DDR2
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config TARGET_MPC8349EMDS_SDRAM
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bool "Support MPC8349EMDS_SDRAM"
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select ARCH_MPC8349
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select BOARD_EARLY_INIT_F
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select SYS_FSL_DDR
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select SYS_FSL_DDR_BE
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select SYS_FSL_HAS_DDR2
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config TARGET_MPC837XERDB
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config TARGET_MPC837XERDB
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bool "Support MPC837XERDB"
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bool "Support MPC837XERDB"
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select ARCH_MPC837X
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select ARCH_MPC837X
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@ -173,15 +157,6 @@ config ARCH_MPC834X
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bool
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bool
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select SYS_CACHE_SHIFT_5
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select SYS_CACHE_SHIFT_5
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config ARCH_MPC8349
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bool
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select ARCH_MPC834X
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select MPC83XX_PCI_SUPPORT
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select MPC83XX_TSEC1_SUPPORT
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select MPC83XX_TSEC2_SUPPORT
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select MPC83XX_LDP_PIN
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select MPC83XX_SECOND_I2C
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config ARCH_MPC8360
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config ARCH_MPC8360
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bool
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bool
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select MPC83XX_QUICC_ENGINE
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select MPC83XX_QUICC_ENGINE
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@ -220,36 +195,9 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
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source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
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menu "Legacy options"
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if ARCH_MPC8349
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#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
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choice
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prompt "PMC slot configuration"
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config PCI_ALL_PCI1
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bool "All PMC slots on PCI1"
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config PCI_ONE_PCI1
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bool "First PMC1 on PCI1"
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config PCI_TWO_PCI1
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bool "First two PMC1 on PCI1"
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endchoice
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config PCI_64BIT
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bool "PMC2 is 64bit"
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endif
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endmenu
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config FSL_ELBC
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config FSL_ELBC
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bool
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bool
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source "board/freescale/mpc8349emds/Kconfig"
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source "board/freescale/mpc837xerdb/Kconfig"
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source "board/freescale/mpc837xerdb/Kconfig"
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source "board/ids/ids8313/Kconfig"
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source "board/ids/ids8313/Kconfig"
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source "board/keymile/Kconfig"
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source "board/keymile/Kconfig"
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@ -22,7 +22,7 @@ config BR0_PORTSIZE_16BIT
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config BR0_PORTSIZE_32BIT
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config BR0_PORTSIZE_32BIT
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depends on !BR0_MACHINE_FCM
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depends on !BR0_MACHINE_FCM
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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depends on ARCH_MPC8360 || ARCH_MPC8379
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bool "32-bit"
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bool "32-bit"
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endchoice
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endchoice
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@ -58,11 +58,11 @@ config BR0_MACHINE_GPCM
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bool "GPCM"
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bool "GPCM"
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config BR0_MACHINE_FCM
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config BR0_MACHINE_FCM
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depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
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depends on !ARCH_MPC832X && !ARCH_MPC8360
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bool "FCM"
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bool "FCM"
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config BR0_MACHINE_SDRAM
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config BR0_MACHINE_SDRAM
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depends on ARCH_MPC8349 || ARCH_MPC8360
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depends on ARCH_MPC8360
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bool "SDRAM"
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bool "SDRAM"
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config BR0_MACHINE_UPMA
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config BR0_MACHINE_UPMA
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@ -22,7 +22,7 @@ config BR1_PORTSIZE_16BIT
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config BR1_PORTSIZE_32BIT
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config BR1_PORTSIZE_32BIT
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depends on !BR1_MACHINE_FCM
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depends on !BR1_MACHINE_FCM
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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depends on ARCH_MPC8360 || ARCH_MPC8379
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bool "32-bit"
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bool "32-bit"
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endchoice
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endchoice
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@ -58,11 +58,11 @@ config BR1_MACHINE_GPCM
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bool "GPCM"
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bool "GPCM"
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config BR1_MACHINE_FCM
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config BR1_MACHINE_FCM
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depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
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depends on !ARCH_MPC832X && !ARCH_MPC8360
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bool "FCM"
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bool "FCM"
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config BR1_MACHINE_SDRAM
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config BR1_MACHINE_SDRAM
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depends on ARCH_MPC8349 || ARCH_MPC8360
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depends on ARCH_MPC8360
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bool "SDRAM"
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bool "SDRAM"
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config BR1_MACHINE_UPMA
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config BR1_MACHINE_UPMA
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@ -22,7 +22,7 @@ config BR2_PORTSIZE_16BIT
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config BR2_PORTSIZE_32BIT
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config BR2_PORTSIZE_32BIT
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depends on !BR2_MACHINE_FCM
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depends on !BR2_MACHINE_FCM
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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depends on ARCH_MPC8360 || ARCH_MPC8379
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bool "32-bit"
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bool "32-bit"
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endchoice
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endchoice
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@ -58,11 +58,11 @@ config BR2_MACHINE_GPCM
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bool "GPCM"
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bool "GPCM"
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config BR2_MACHINE_FCM
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config BR2_MACHINE_FCM
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depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
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depends on !ARCH_MPC832X && !ARCH_MPC8360
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bool "FCM"
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bool "FCM"
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config BR2_MACHINE_SDRAM
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config BR2_MACHINE_SDRAM
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depends on ARCH_MPC8349 || ARCH_MPC8360
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depends on ARCH_MPC8360
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bool "SDRAM"
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bool "SDRAM"
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config BR2_MACHINE_UPMA
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config BR2_MACHINE_UPMA
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@ -22,7 +22,7 @@ config BR3_PORTSIZE_16BIT
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config BR3_PORTSIZE_32BIT
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config BR3_PORTSIZE_32BIT
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depends on !BR3_MACHINE_FCM
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depends on !BR3_MACHINE_FCM
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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depends on ARCH_MPC8360 || ARCH_MPC8379
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bool "32-bit"
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bool "32-bit"
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endchoice
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endchoice
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@ -58,11 +58,11 @@ config BR3_MACHINE_GPCM
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bool "GPCM"
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bool "GPCM"
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config BR3_MACHINE_FCM
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config BR3_MACHINE_FCM
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depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
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depends on !ARCH_MPC832X && !ARCH_MPC8360
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bool "FCM"
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bool "FCM"
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config BR3_MACHINE_SDRAM
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config BR3_MACHINE_SDRAM
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depends on ARCH_MPC8349 || ARCH_MPC8360
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depends on ARCH_MPC8360
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bool "SDRAM"
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bool "SDRAM"
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config BR3_MACHINE_UPMA
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config BR3_MACHINE_UPMA
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@ -22,7 +22,7 @@ config BR4_PORTSIZE_16BIT
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config BR4_PORTSIZE_32BIT
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config BR4_PORTSIZE_32BIT
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depends on !BR4_MACHINE_FCM
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depends on !BR4_MACHINE_FCM
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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depends on ARCH_MPC8360 || ARCH_MPC8379
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bool "32-bit"
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bool "32-bit"
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endchoice
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endchoice
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@ -58,11 +58,11 @@ config BR4_MACHINE_GPCM
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bool "GPCM"
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bool "GPCM"
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config BR4_MACHINE_FCM
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config BR4_MACHINE_FCM
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depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
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depends on !ARCH_MPC832X && !ARCH_MPC8360
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bool "FCM"
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bool "FCM"
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config BR4_MACHINE_SDRAM
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config BR4_MACHINE_SDRAM
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depends on ARCH_MPC8349 || ARCH_MPC8360
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depends on ARCH_MPC8360
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bool "SDRAM"
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bool "SDRAM"
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config BR4_MACHINE_UPMA
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config BR4_MACHINE_UPMA
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@ -434,7 +434,7 @@ config HID2_IWLCK_1
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config HID2_IWLCK_2
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config HID2_IWLCK_2
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bool "Way 0 through 2 locked"
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bool "Way 0 through 2 locked"
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if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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if ARCH_MPC8360 || ARCH_MPC8379
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config HID2_IWLCK_3
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config HID2_IWLCK_3
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bool "Way 0 through 3 locked"
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bool "Way 0 through 3 locked"
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@ -470,7 +470,7 @@ config HID2_DWLCK_1
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config HID2_DWLCK_2
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config HID2_DWLCK_2
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bool "Way 0 through 2 locked"
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bool "Way 0 through 2 locked"
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if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
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if ARCH_MPC8360 || ARCH_MPC8379
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config HID2_DWLCK_3
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config HID2_DWLCK_3
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bool "Way 0 through 3 locked"
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bool "Way 0 through 3 locked"
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@ -7,7 +7,7 @@ config LBMC_CLOCK_MODE_1_1
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bool "1 : 1"
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bool "1 : 1"
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config LBMC_CLOCK_MODE_1_2
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config LBMC_CLOCK_MODE_1_2
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
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depends on ARCH_MPC8360 || ARCH_MPC837X
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bool "1 : 2"
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bool "1 : 2"
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endchoice
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endchoice
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@ -19,12 +19,12 @@ config DDR_MC_CLOCK_MODE_1_2
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bool "1 : 2"
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bool "1 : 2"
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config DDR_MC_CLOCK_MODE_1_1
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config DDR_MC_CLOCK_MODE_1_1
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depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
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depends on ARCH_MPC8360 || ARCH_MPC837X
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bool "1 : 1"
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bool "1 : 1"
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endchoice
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endchoice
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if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349
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if !ARCH_MPC8313 && !ARCH_MPC832X
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choice
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choice
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prompt "System PLL VCO division"
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prompt "System PLL VCO division"
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@ -67,43 +67,43 @@ config SYSTEM_PLL_FACTOR_6_1
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bool "6 : 1"
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bool "6 : 1"
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config SYSTEM_PLL_FACTOR_7_1
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config SYSTEM_PLL_FACTOR_7_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "7 : 1"
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bool "7 : 1"
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config SYSTEM_PLL_FACTOR_8_1
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config SYSTEM_PLL_FACTOR_8_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "8 : 1"
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bool "8 : 1"
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config SYSTEM_PLL_FACTOR_9_1
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config SYSTEM_PLL_FACTOR_9_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "9 : 1"
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bool "9 : 1"
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config SYSTEM_PLL_FACTOR_10_1
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config SYSTEM_PLL_FACTOR_10_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "10 : 1"
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bool "10 : 1"
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config SYSTEM_PLL_FACTOR_11_1
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config SYSTEM_PLL_FACTOR_11_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "11 : 1"
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bool "11 : 1"
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config SYSTEM_PLL_FACTOR_12_1
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config SYSTEM_PLL_FACTOR_12_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "12 : 1"
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bool "12 : 1"
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config SYSTEM_PLL_FACTOR_13_1
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config SYSTEM_PLL_FACTOR_13_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "13 : 1"
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bool "13 : 1"
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config SYSTEM_PLL_FACTOR_14_1
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config SYSTEM_PLL_FACTOR_14_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "14 : 1"
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bool "14 : 1"
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config SYSTEM_PLL_FACTOR_15_1
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config SYSTEM_PLL_FACTOR_15_1
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depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X
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depends on ARCH_MPV8360 || ARCH_MPC837X
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bool "15 : 1"
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bool "15 : 1"
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config SYSTEM_PLL_FACTOR_16_1
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config SYSTEM_PLL_FACTOR_16_1
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depends on ARCH_MPC8349 || ARCH_MPV8360
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depends on ARCH_MPV8360
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bool "16 : 1"
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bool "16 : 1"
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endchoice
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endchoice
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@ -310,21 +310,6 @@ config PCI_HOST_MODE_ENABLE
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endchoice
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endchoice
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if ARCH_MPC8349
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choice
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prompt "PCI 64-bit mode"
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config PCI_64BIT_MODE_DISABLE
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bool "Disabled"
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config PCI_64BIT_MODE_ENABLE
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bool "Enabled"
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endchoice
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endif
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choice
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choice
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prompt "PCI internal arbiter 1 mode"
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prompt "PCI internal arbiter 1 mode"
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@ -336,21 +321,6 @@ config PCI_INT_ARBITER1_ENABLE
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endchoice
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endchoice
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if ARCH_MPC8349
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choice
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prompt "PCI internal arbiter 2 mode"
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config PCI_INT_ARBITER2_DISABLE
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bool "Disabled"
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config PCI_INT_ARBITER2_ENABLE
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bool "Enabled"
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endchoice
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endif
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if ARCH_MPC8360
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if ARCH_MPC8360
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choice
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choice
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@ -425,10 +395,6 @@ config BOOT_ROM_INTERFACE_PCI1
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depends on MPC83XX_PCI_SUPPORT
|
depends on MPC83XX_PCI_SUPPORT
|
||||||
bool "PCI1"
|
bool "PCI1"
|
||||||
|
|
||||||
config BOOT_ROM_INTERFACE_PCI2
|
|
||||||
depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
|
|
||||||
bool "PCI2"
|
|
||||||
|
|
||||||
config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
|
config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
|
||||||
depends on ARCH_MPC837X
|
depends on ARCH_MPC837X
|
||||||
bool "PCI2"
|
bool "PCI2"
|
||||||
|
|
@ -448,15 +414,15 @@ config BOOT_ROM_INTERFACE_GPCM_16BIT
|
||||||
bool "Local bus GPCM - 16-bit ROM"
|
bool "Local bus GPCM - 16-bit ROM"
|
||||||
|
|
||||||
config BOOT_ROM_INTERFACE_GPCM_32BIT
|
config BOOT_ROM_INTERFACE_GPCM_32BIT
|
||||||
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
|
depends on ARCH_MPC8360 || ARCH_MPC837X
|
||||||
bool "Local bus GPCM - 32-bit ROM"
|
bool "Local bus GPCM - 32-bit ROM"
|
||||||
|
|
||||||
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
|
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
|
||||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
depends on !ARCH_MPC832X && !ARCH_MPC8360
|
||||||
bool "Local bus NAND Flash- 8-bit small page ROM"
|
bool "Local bus NAND Flash- 8-bit small page ROM"
|
||||||
|
|
||||||
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
|
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
|
||||||
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
|
depends on !ARCH_MPC832X && !ARCH_MPC8360
|
||||||
bool "Local bus NAND Flash- 8-bit large page ROM"
|
bool "Local bus NAND Flash- 8-bit large page ROM"
|
||||||
|
|
||||||
endchoice
|
endchoice
|
||||||
|
|
@ -467,11 +433,10 @@ choice
|
||||||
prompt "TSEC1 mode"
|
prompt "TSEC1 mode"
|
||||||
|
|
||||||
config TSEC1_MODE_MII
|
config TSEC1_MODE_MII
|
||||||
depends on !ARCH_MPC8349
|
|
||||||
bool "MII"
|
bool "MII"
|
||||||
|
|
||||||
config TSEC1_MODE_RMII
|
config TSEC1_MODE_RMII
|
||||||
depends on ARCH_MPC831X && !ARCH_MPC8349
|
depends on ARCH_MPC831X
|
||||||
bool "RMII"
|
bool "RMII"
|
||||||
|
|
||||||
config TSEC1_MODE_RGMII
|
config TSEC1_MODE_RGMII
|
||||||
|
|
@ -481,14 +446,6 @@ config TSEC1_MODE_RTBI
|
||||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||||
bool "RTBI"
|
bool "RTBI"
|
||||||
|
|
||||||
config TSEC1_MODE_GMII
|
|
||||||
depends on ARCH_MPC8349
|
|
||||||
bool "GMII"
|
|
||||||
|
|
||||||
config TSEC1_MODE_TBI
|
|
||||||
depends on ARCH_MPC8349
|
|
||||||
bool "TBI"
|
|
||||||
|
|
||||||
config TSEC1_MODE_SGMII
|
config TSEC1_MODE_SGMII
|
||||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||||
bool "SGMII"
|
bool "SGMII"
|
||||||
|
|
@ -503,11 +460,10 @@ choice
|
||||||
prompt "TSEC2 mode"
|
prompt "TSEC2 mode"
|
||||||
|
|
||||||
config TSEC2_MODE_MII
|
config TSEC2_MODE_MII
|
||||||
depends on !ARCH_MPC8349
|
|
||||||
bool "MII"
|
bool "MII"
|
||||||
|
|
||||||
config TSEC2_MODE_RMII
|
config TSEC2_MODE_RMII
|
||||||
depends on ARCH_MPC831X && !ARCH_MPC8349
|
depends on ARCH_MPC831X
|
||||||
bool "RMII"
|
bool "RMII"
|
||||||
|
|
||||||
config TSEC2_MODE_RGMII
|
config TSEC2_MODE_RGMII
|
||||||
|
|
@ -517,14 +473,6 @@ config TSEC2_MODE_RTBI
|
||||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||||
bool "RTBI"
|
bool "RTBI"
|
||||||
|
|
||||||
config TSEC2_MODE_GMII
|
|
||||||
depends on ARCH_MPC8349
|
|
||||||
bool "GMII"
|
|
||||||
|
|
||||||
config TSEC2_MODE_TBI
|
|
||||||
depends on ARCH_MPC8349
|
|
||||||
bool "TBI"
|
|
||||||
|
|
||||||
config TSEC2_MODE_SGMII
|
config TSEC2_MODE_SGMII
|
||||||
depends on ARCH_MPC831X || ARCH_MPC837X
|
depends on ARCH_MPC831X || ARCH_MPC837X
|
||||||
bool "SGMII"
|
bool "SGMII"
|
||||||
|
|
@ -559,7 +507,7 @@ endchoice
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360
|
if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "LALE timing"
|
prompt "LALE timing"
|
||||||
|
|
@ -603,7 +551,7 @@ config DDR_MC_CLOCK_MODE
|
||||||
|
|
||||||
config SYSTEM_PLL_VCO_DIV
|
config SYSTEM_PLL_VCO_DIV
|
||||||
int
|
int
|
||||||
default 0 if ARCH_MPC8349 || ARCH_MPC832X
|
default 0 if ARCH_MPC832X
|
||||||
default 2 if ARCH_MPC8313
|
default 2 if ARCH_MPC8313
|
||||||
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
|
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
|
||||||
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
|
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
|
||||||
|
|
@ -675,7 +623,6 @@ config BOOT_ROM_INTERFACE
|
||||||
hex
|
hex
|
||||||
default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
|
default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
|
||||||
default 0x4 if BOOT_ROM_INTERFACE_PCI1
|
default 0x4 if BOOT_ROM_INTERFACE_PCI1
|
||||||
default 0x8 if BOOT_ROM_INTERFACE_PCI2
|
|
||||||
default 0x8 if BOOT_ROM_INTERFACE_ESDHC
|
default 0x8 if BOOT_ROM_INTERFACE_ESDHC
|
||||||
default 0xc if BOOT_ROM_INTERFACE_SPI
|
default 0xc if BOOT_ROM_INTERFACE_SPI
|
||||||
default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
|
default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
|
||||||
|
|
@ -690,26 +637,18 @@ config TSEC1_MODE
|
||||||
default 0x0 if !MPC83XX_TSEC1_SUPPORT
|
default 0x0 if !MPC83XX_TSEC1_SUPPORT
|
||||||
default 0x0 if TSEC1_MODE_MII
|
default 0x0 if TSEC1_MODE_MII
|
||||||
default 0x1 if TSEC1_MODE_RMII
|
default 0x1 if TSEC1_MODE_RMII
|
||||||
default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349
|
default 0x3 if TSEC1_MODE_RGMII
|
||||||
default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349
|
default 0x5 if TSEC1_MODE_RTBI
|
||||||
default 0x6 if TSEC1_MODE_SGMII
|
default 0x6 if TSEC1_MODE_SGMII
|
||||||
default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
|
|
||||||
default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
|
|
||||||
default 0x2 if TSEC1_MODE_GMII
|
|
||||||
default 0x3 if TSEC1_MODE_TBI
|
|
||||||
|
|
||||||
config TSEC2_MODE
|
config TSEC2_MODE
|
||||||
hex
|
hex
|
||||||
default 0x0 if !MPC83XX_TSEC2_SUPPORT
|
default 0x0 if !MPC83XX_TSEC2_SUPPORT
|
||||||
default 0x0 if TSEC2_MODE_MII
|
default 0x0 if TSEC2_MODE_MII
|
||||||
default 0x1 if TSEC2_MODE_RMII
|
default 0x1 if TSEC2_MODE_RMII
|
||||||
default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349
|
default 0x3 if TSEC2_MODE_RGMII
|
||||||
default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349
|
default 0x5 if TSEC2_MODE_RTBI
|
||||||
default 0x6 if TSEC2_MODE_SGMII
|
default 0x6 if TSEC2_MODE_SGMII
|
||||||
default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
|
|
||||||
default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
|
|
||||||
default 0x2 if TSEC2_MODE_GMII
|
|
||||||
default 0x3 if TSEC2_MODE_TBI
|
|
||||||
|
|
||||||
config SECONDARY_DDR_IO
|
config SECONDARY_DDR_IO
|
||||||
int
|
int
|
||||||
|
|
@ -792,9 +731,7 @@ config PCI_HOST_MODE
|
||||||
|
|
||||||
config PCI_64BIT_MODE
|
config PCI_64BIT_MODE
|
||||||
int
|
int
|
||||||
default 0 if !ARCH_MPC8349
|
default 0
|
||||||
default 0 if PCI_64BIT_MODE_DISABLE
|
|
||||||
default 1 if PCI_64BIT_MODE_ENABLE
|
|
||||||
|
|
||||||
config PCI_INT_ARBITER1
|
config PCI_INT_ARBITER1
|
||||||
int
|
int
|
||||||
|
|
@ -804,9 +741,7 @@ config PCI_INT_ARBITER1
|
||||||
|
|
||||||
config PCI_INT_ARBITER2
|
config PCI_INT_ARBITER2
|
||||||
int
|
int
|
||||||
default 0 if !ARCH_MPC8349
|
default 0
|
||||||
default 0 if PCI_INT_ARBITER2_DISABLE
|
|
||||||
default 1 if PCI_INT_ARBITER2_ENABLE
|
|
||||||
|
|
||||||
config PCI_CLOCK_OUTPUT_DRIVE
|
config PCI_CLOCK_OUTPUT_DRIVE
|
||||||
int
|
int
|
||||||
|
|
|
||||||
|
|
@ -1,11 +1,3 @@
|
||||||
#ifdef CONFIG_ARCH_MPC8349
|
|
||||||
#define TSEC1_MODE_SHIFT 17
|
|
||||||
#define TSEC2_MODE_SHIFT 19
|
|
||||||
#else
|
|
||||||
#define TSEC1_MODE_SHIFT 18
|
|
||||||
#define TSEC2_MODE_SHIFT 21
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_HRCW_LOW (\
|
#define CONFIG_SYS_HRCW_LOW (\
|
||||||
(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
|
(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
|
||||||
(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
|
(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
|
||||||
|
|
@ -28,8 +20,8 @@
|
||||||
(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
|
(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
|
||||||
(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
|
(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
|
||||||
(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
|
(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
|
||||||
(CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
|
(CONFIG_TSEC1_MODE << (31 - 18)) |\
|
||||||
(CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
|
(CONFIG_TSEC2_MODE << (31 - 21)) |\
|
||||||
(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
|
(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
|
||||||
(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
|
(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
|
||||||
(CONFIG_LALE_TIMING << (31 - 29)) |\
|
(CONFIG_LALE_TIMING << (31 - 29)) |\
|
||||||
|
|
|
||||||
|
|
@ -38,50 +38,6 @@ endchoice
|
||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if ARCH_MPC8349
|
|
||||||
|
|
||||||
choice
|
|
||||||
prompt "TSEC1 emergency priority"
|
|
||||||
|
|
||||||
config SPCR_TSEC1EP_UNSET
|
|
||||||
bool "Don't set value"
|
|
||||||
|
|
||||||
config SPCR_TSEC1EP_0
|
|
||||||
bool "Level 0 (lowest priority)"
|
|
||||||
|
|
||||||
config SPCR_TSEC1EP_1
|
|
||||||
bool "Level 1"
|
|
||||||
|
|
||||||
config SPCR_TSEC1EP_2
|
|
||||||
bool "Level 2"
|
|
||||||
|
|
||||||
config SPCR_TSEC1EP_3
|
|
||||||
bool "Level 3 (highest priority)"
|
|
||||||
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
choice
|
|
||||||
prompt "TSEC2 emergency priority"
|
|
||||||
|
|
||||||
config SPCR_TSEC2EP_UNSET
|
|
||||||
bool "Don't set value"
|
|
||||||
|
|
||||||
config SPCR_TSEC2EP_0
|
|
||||||
bool "Level 0 (lowest priority)"
|
|
||||||
|
|
||||||
config SPCR_TSEC2EP_1
|
|
||||||
bool "Level 1"
|
|
||||||
|
|
||||||
config SPCR_TSEC2EP_2
|
|
||||||
bool "Level 2"
|
|
||||||
|
|
||||||
config SPCR_TSEC2EP_3
|
|
||||||
bool "Level 3 (highest priority)"
|
|
||||||
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
||||||
config SPCR_OPT
|
config SPCR_OPT
|
||||||
hex
|
hex
|
||||||
default 0x0 if SPCR_OPT_UNSET
|
default 0x0 if SPCR_OPT_UNSET
|
||||||
|
|
|
||||||
|
|
@ -1,25 +0,0 @@
|
||||||
if TARGET_MPC8349EMDS
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "mpc8349emds"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "freescale"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "MPC8349EMDS"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
||||||
if TARGET_MPC8349EMDS_SDRAM
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "mpc8349emds"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "freescale"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "MPC8349EMDS_SDRAM"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
MPC8349EMDS BOARD
|
|
||||||
#M: Kim Phillips <kim.phillips@freescale.com>
|
|
||||||
S: Orphan (since 2018-05)
|
|
||||||
F: board/freescale/mpc8349emds/
|
|
||||||
F: include/configs/MPC8349EMDS.h
|
|
||||||
F: configs/MPC8349EMDS_defconfig
|
|
||||||
F: configs/MPC8349EMDS_SDRAM_defconfig
|
|
||||||
F: configs/MPC8349EMDS_PCI64_defconfig
|
|
||||||
F: configs/MPC8349EMDS_SLAVE_defconfig
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# (C) Copyright 2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
|
|
||||||
obj-y += mpc8349emds.o
|
|
||||||
obj-$(CONFIG_PCI) += pci.o
|
|
||||||
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
|
|
||||||
|
|
@ -1,100 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <fsl_ddr_dimm_params.h>
|
|
||||||
|
|
||||||
struct board_specific_parameters {
|
|
||||||
u32 n_ranks;
|
|
||||||
u32 datarate_mhz_high;
|
|
||||||
u32 clk_adjust;
|
|
||||||
u32 cpo;
|
|
||||||
u32 write_data_delay;
|
|
||||||
u32 force_2t;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This table contains all valid speeds we want to override with board
|
|
||||||
* specific parameters. datarate_mhz_high values need to be in ascending order
|
|
||||||
* for each n_ranks group.
|
|
||||||
*/
|
|
||||||
static const struct board_specific_parameters udimm0[] = {
|
|
||||||
/*
|
|
||||||
* memory controller 0
|
|
||||||
* num| hi| clk| cpo|wrdata|2T
|
|
||||||
* ranks| mhz|adjst| | delay|
|
|
||||||
*/
|
|
||||||
{2, 300, 4, 4, 2, 0},
|
|
||||||
{2, 365, 4, 6, 2, 0},
|
|
||||||
{2, 450, 4, 7, 2, 0},
|
|
||||||
{2, 850, 4, 31, 2, 0},
|
|
||||||
{1, 300, 4, 4, 2, 0},
|
|
||||||
{1, 365, 4, 6, 2, 0},
|
|
||||||
{1, 450, 4, 7, 2, 0},
|
|
||||||
{1, 850, 4, 31, 2, 0},
|
|
||||||
{}
|
|
||||||
};
|
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
||||||
dimm_params_t *pdimm,
|
|
||||||
unsigned int ctrl_num)
|
|
||||||
{
|
|
||||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
|
|
||||||
unsigned int i;
|
|
||||||
ulong ddr_freq;
|
|
||||||
|
|
||||||
if (ctrl_num != 0) /* we have only one controller */
|
|
||||||
return;
|
|
||||||
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
|
|
||||||
if (pdimm[i].n_ranks)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
|
|
||||||
return;
|
|
||||||
|
|
||||||
pbsp = udimm0;
|
|
||||||
|
|
||||||
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
|
|
||||||
* freqency and n_banks specified in board_specific_parameters table.
|
|
||||||
*/
|
|
||||||
ddr_freq = get_ddr_freq(0) / 1000000;
|
|
||||||
while (pbsp->datarate_mhz_high) {
|
|
||||||
if (pbsp->n_ranks == pdimm[i].n_ranks) {
|
|
||||||
if (ddr_freq <= pbsp->datarate_mhz_high) {
|
|
||||||
popts->clk_adjust = pbsp->clk_adjust;
|
|
||||||
popts->cpo_override = pbsp->cpo;
|
|
||||||
popts->write_data_delay =
|
|
||||||
pbsp->write_data_delay;
|
|
||||||
popts->twot_en = pbsp->force_2t;
|
|
||||||
goto found;
|
|
||||||
}
|
|
||||||
pbsp_highest = pbsp;
|
|
||||||
}
|
|
||||||
pbsp++;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pbsp_highest) {
|
|
||||||
printf("Error: board specific timing not found "
|
|
||||||
"for data rate %lu MT/s!\n"
|
|
||||||
"Trying to use the highest speed (%u) parameters\n",
|
|
||||||
ddr_freq, pbsp_highest->datarate_mhz_high);
|
|
||||||
popts->clk_adjust = pbsp_highest->clk_adjust;
|
|
||||||
popts->cpo_override = pbsp_highest->cpo;
|
|
||||||
popts->write_data_delay = pbsp_highest->write_data_delay;
|
|
||||||
popts->twot_en = pbsp_highest->force_2t;
|
|
||||||
} else {
|
|
||||||
panic("DIMM is not supported by this board");
|
|
||||||
}
|
|
||||||
|
|
||||||
found:
|
|
||||||
/*
|
|
||||||
* Factors to consider for half-strength driver enable:
|
|
||||||
* - number of DIMMs installed
|
|
||||||
*/
|
|
||||||
popts->half_strength_driver_enable = 0;
|
|
||||||
popts->dqs_config = 0; /* only true DQS signal is used on board */
|
|
||||||
}
|
|
||||||
|
|
@ -1,277 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2006
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <ioports.h>
|
|
||||||
#include <mpc83xx.h>
|
|
||||||
#include <asm/bitops.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/mpc8349_pci.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
#include <spi.h>
|
|
||||||
#include <miiphy.h>
|
|
||||||
#ifdef CONFIG_SYS_FSL_DDR2
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#else
|
|
||||||
#include <spd_sdram.h>
|
|
||||||
#endif
|
|
||||||
#include <linux/delay.h>
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_LIBFDT)
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
int fixed_sdram(void);
|
|
||||||
void sdram_init(void);
|
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
|
|
||||||
void ddr_enable_ecc(unsigned int dram_size);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
int board_early_init_f (void)
|
|
||||||
{
|
|
||||||
volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
|
|
||||||
|
|
||||||
/* Enable flash write */
|
|
||||||
bcsr[1] &= ~0x01;
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
|
|
||||||
/* Use USB PHY on SYS board */
|
|
||||||
bcsr[5] |= 0x02;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int dram_init(void)
|
|
||||||
{
|
|
||||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
phys_size_t msize = 0;
|
|
||||||
|
|
||||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
|
|
||||||
return -ENXIO;
|
|
||||||
|
|
||||||
/* DDR SDRAM - Main SODIMM */
|
|
||||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
#ifndef CONFIG_SYS_FSL_DDR2
|
|
||||||
msize = spd_sdram() * 1024 * 1024;
|
|
||||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
|
||||||
ddr_enable_ecc(msize);
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
msize = fsl_ddr_sdram();
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
msize = fixed_sdram() * 1024 * 1024;
|
|
||||||
#endif
|
|
||||||
/*
|
|
||||||
* Initialize SDRAM if it is on local bus.
|
|
||||||
*/
|
|
||||||
sdram_init();
|
|
||||||
|
|
||||||
/* set total bus SDRAM size(bytes) -- DDR */
|
|
||||||
gd->ram_size = msize;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM)
|
|
||||||
/*************************************************************************
|
|
||||||
* fixed sdram init -- doesn't use serial presence detect.
|
|
||||||
************************************************************************/
|
|
||||||
int fixed_sdram(void)
|
|
||||||
{
|
|
||||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
u32 msize = CONFIG_SYS_DDR_SIZE;
|
|
||||||
u32 ddr_size = msize << 20; /* DDR size in bytes */
|
|
||||||
u32 ddr_size_log2 = __ilog2(ddr_size);
|
|
||||||
|
|
||||||
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
|
|
||||||
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_DDR_SIZE != 256)
|
|
||||||
#warning Currenly any ddr size other than 256 is not supported
|
|
||||||
#endif
|
|
||||||
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
|
|
||||||
#warning Chip select bounds is only configurable in 16MB increments
|
|
||||||
#endif
|
|
||||||
im->ddr.csbnds[2].csbnds =
|
|
||||||
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
|
|
||||||
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
|
|
||||||
CSBNDS_EA_SHIFT) & CSBNDS_EA);
|
|
||||||
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
|
|
||||||
|
|
||||||
/* currently we use only one CS, so disable the other banks */
|
|
||||||
im->ddr.cs_config[0] = 0;
|
|
||||||
im->ddr.cs_config[1] = 0;
|
|
||||||
im->ddr.cs_config[3] = 0;
|
|
||||||
|
|
||||||
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
|
|
||||||
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
|
|
||||||
|
|
||||||
im->ddr.sdram_cfg =
|
|
||||||
SDRAM_CFG_SREN
|
|
||||||
| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
|
|
||||||
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
|
|
||||||
|
|
||||||
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
|
|
||||||
udelay(200);
|
|
||||||
|
|
||||||
/* enable DDR controller */
|
|
||||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
|
|
||||||
return msize;
|
|
||||||
}
|
|
||||||
#endif/*!CONFIG_SYS_SPD_EEPROM*/
|
|
||||||
|
|
||||||
|
|
||||||
int checkboard (void)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Warning: do not read the BCSR registers here
|
|
||||||
*
|
|
||||||
* There is a timing bug in the 8349E and 8349EA BCSR code
|
|
||||||
* version 1.2 (read from BCSR 11) that will cause the CFI
|
|
||||||
* flash initialization code to overwrite BCSR 0, disabling
|
|
||||||
* the serial ports and gigabit ethernet
|
|
||||||
*/
|
|
||||||
|
|
||||||
puts("Board: Freescale MPC8349EMDS\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* if MPC8349EMDS is soldered with SDRAM
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_SYS_BR2_PRELIM) \
|
|
||||||
&& defined(CONFIG_SYS_OR2_PRELIM) \
|
|
||||||
&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
|
|
||||||
&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
|
|
||||||
/*
|
|
||||||
* Initialize SDRAM memory on the Local Bus.
|
|
||||||
*/
|
|
||||||
|
|
||||||
void sdram_init(void)
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
volatile fsl_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
|
|
||||||
const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
|
|
||||||
LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
|
|
||||||
LSDMR_WRC3 | LSDMR_CL3;
|
|
||||||
/*
|
|
||||||
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* setup mtrpt, lsrt and lbcr for LB bus */
|
|
||||||
lbc->lbcr = 0x00000000;
|
|
||||||
/* LB refresh timer prescal, 266MHz/32 */
|
|
||||||
lbc->mrtpr = 0x20000000;
|
|
||||||
/* LB sdram refresh timer, about 6us */
|
|
||||||
lbc->lsrt = 0x32000000;
|
|
||||||
asm("sync");
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure the SDRAM controller Machine Mode Register.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* 0x40636733; normal operation */
|
|
||||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
|
|
||||||
|
|
||||||
/* 0x68636733; precharge all the banks */
|
|
||||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
|
|
||||||
asm("sync");
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
|
|
||||||
/* 0x48636733; auto refresh */
|
|
||||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
|
|
||||||
asm("sync");
|
|
||||||
/*1 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
/*2 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
/*3 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
/*4 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
/*5 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
/*6 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
/*7 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
/*8 times*/
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
|
|
||||||
/* 0x58636733; mode register write operation */
|
|
||||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
|
|
||||||
asm("sync");
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
|
|
||||||
/* 0x40636733; normal operation */
|
|
||||||
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
|
|
||||||
asm("sync");
|
|
||||||
*sdram_addr = 0xff;
|
|
||||||
udelay(100);
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
void sdram_init(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The following are used to control the SPI chip selects for the SPI command.
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_MPC8XXX_SPI
|
|
||||||
|
|
||||||
#define SPI_CS_MASK 0x80000000
|
|
||||||
|
|
||||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|
||||||
{
|
|
||||||
return bus == 0 && cs == 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_cs_activate(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
|
|
||||||
|
|
||||||
iopd->dat &= ~SPI_CS_MASK;
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_cs_deactivate(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
|
|
||||||
|
|
||||||
iopd->dat |= SPI_CS_MASK;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
ft_pci_setup(blob, bd);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,118 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <init.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <mpc83xx.h>
|
|
||||||
#include <pci.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
#include <asm/fsl_i2c.h>
|
|
||||||
#include <linux/delay.h>
|
|
||||||
|
|
||||||
static struct pci_region pci1_regions[] = {
|
|
||||||
{
|
|
||||||
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
|
|
||||||
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
|
|
||||||
size: CONFIG_SYS_PCI1_MEM_SIZE,
|
|
||||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
|
||||||
},
|
|
||||||
{
|
|
||||||
bus_start: CONFIG_SYS_PCI1_IO_BASE,
|
|
||||||
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
|
|
||||||
size: CONFIG_SYS_PCI1_IO_SIZE,
|
|
||||||
flags: PCI_REGION_IO
|
|
||||||
},
|
|
||||||
{
|
|
||||||
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
|
|
||||||
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
|
|
||||||
size: CONFIG_SYS_PCI1_MMIO_SIZE,
|
|
||||||
flags: PCI_REGION_MEM
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef CONFIG_MPC83XX_PCI2
|
|
||||||
static struct pci_region pci2_regions[] = {
|
|
||||||
{
|
|
||||||
bus_start: CONFIG_SYS_PCI2_MEM_BASE,
|
|
||||||
phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
|
|
||||||
size: CONFIG_SYS_PCI2_MEM_SIZE,
|
|
||||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
|
||||||
},
|
|
||||||
{
|
|
||||||
bus_start: CONFIG_SYS_PCI2_IO_BASE,
|
|
||||||
phys_start: CONFIG_SYS_PCI2_IO_PHYS,
|
|
||||||
size: CONFIG_SYS_PCI2_IO_SIZE,
|
|
||||||
flags: PCI_REGION_IO
|
|
||||||
},
|
|
||||||
{
|
|
||||||
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
|
|
||||||
phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
|
|
||||||
size: CONFIG_SYS_PCI2_MMIO_SIZE,
|
|
||||||
flags: PCI_REGION_MEM
|
|
||||||
},
|
|
||||||
};
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef CONFIG_PCISLAVE
|
|
||||||
void pib_init(void)
|
|
||||||
{
|
|
||||||
u8 val8, orig_i2c_bus;
|
|
||||||
/*
|
|
||||||
* Assign PIB PMC slot to desired PCI bus
|
|
||||||
*/
|
|
||||||
/* Switch temporarily to I2C bus #2 */
|
|
||||||
orig_i2c_bus = i2c_get_bus_num();
|
|
||||||
i2c_set_bus_num(1);
|
|
||||||
|
|
||||||
val8 = 0;
|
|
||||||
i2c_write(0x23, 0x6, 1, &val8, 1);
|
|
||||||
i2c_write(0x23, 0x7, 1, &val8, 1);
|
|
||||||
val8 = 0xff;
|
|
||||||
i2c_write(0x23, 0x2, 1, &val8, 1);
|
|
||||||
i2c_write(0x23, 0x3, 1, &val8, 1);
|
|
||||||
|
|
||||||
val8 = 0;
|
|
||||||
i2c_write(0x26, 0x6, 1, &val8, 1);
|
|
||||||
val8 = 0x34;
|
|
||||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
|
||||||
#if defined(CONFIG_PCI_64BIT)
|
|
||||||
val8 = 0xf4; /* PMC2:PCI1/64-bit */
|
|
||||||
#elif defined(CONFIG_PCI_ALL_PCI1)
|
|
||||||
val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
|
|
||||||
#elif defined(CONFIG_PCI_ONE_PCI1)
|
|
||||||
val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
|
|
||||||
#else
|
|
||||||
val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
|
|
||||||
#endif
|
|
||||||
i2c_write(0x26, 0x2, 1, &val8, 1);
|
|
||||||
val8 = 0xff;
|
|
||||||
i2c_write(0x26, 0x3, 1, &val8, 1);
|
|
||||||
val8 = 0;
|
|
||||||
i2c_write(0x27, 0x6, 1, &val8, 1);
|
|
||||||
i2c_write(0x27, 0x7, 1, &val8, 1);
|
|
||||||
val8 = 0xff;
|
|
||||||
i2c_write(0x27, 0x2, 1, &val8, 1);
|
|
||||||
val8 = 0xef;
|
|
||||||
i2c_write(0x27, 0x3, 1, &val8, 1);
|
|
||||||
asm("eieio");
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI_64BIT)
|
|
||||||
printf("PCI1: 64-bit on PMC2\n");
|
|
||||||
#elif defined(CONFIG_PCI_ALL_PCI1)
|
|
||||||
printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
|
|
||||||
#elif defined(CONFIG_PCI_ONE_PCI1)
|
|
||||||
printf("PCI1: 32-bit on PMC1\n");
|
|
||||||
printf("PCI2: 32-bit on PMC2, PMC3\n");
|
|
||||||
#else
|
|
||||||
printf("PCI1: 32-bit on PMC1, PMC2\n");
|
|
||||||
printf("PCI2: 32-bit on PMC3\n");
|
|
||||||
#endif
|
|
||||||
/* Reset to original I2C bus */
|
|
||||||
i2c_set_bus_num(orig_i2c_bus);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_PCISLAVE */
|
|
||||||
|
|
@ -1,127 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xFE000000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_SYS_MALLOC_LEN=0x40000
|
|
||||||
CONFIG_SYS_CLK_FREQ=66000000
|
|
||||||
CONFIG_MPC83xx=y
|
|
||||||
CONFIG_HIGH_BATS=y
|
|
||||||
CONFIG_TARGET_MPC8349EMDS=y
|
|
||||||
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
|
|
||||||
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
|
|
||||||
CONFIG_CORE_PLL_RATIO_2_1=y
|
|
||||||
CONFIG_PCI_HOST_MODE_ENABLE=y
|
|
||||||
CONFIG_PCI_64BIT_MODE_ENABLE=y
|
|
||||||
CONFIG_PCI_INT_ARBITER1_ENABLE=y
|
|
||||||
CONFIG_BOOT_MEMORY_SPACE_LOW=y
|
|
||||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
||||||
CONFIG_TSEC1_MODE_GMII=y
|
|
||||||
CONFIG_TSEC2_MODE_GMII=y
|
|
||||||
CONFIG_BAT0=y
|
|
||||||
CONFIG_BAT0_NAME="SDRAM"
|
|
||||||
CONFIG_BAT0_BASE=0x00000000
|
|
||||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT0_ACCESS_RW=y
|
|
||||||
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT5=y
|
|
||||||
CONFIG_BAT5_NAME="IMMR"
|
|
||||||
CONFIG_BAT5_BASE=0xE0000000
|
|
||||||
CONFIG_BAT5_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT5_ACCESS_RW=y
|
|
||||||
CONFIG_BAT5_ICACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_DCACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT6=y
|
|
||||||
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
|
|
||||||
CONFIG_BAT6_BASE=0xF0000000
|
|
||||||
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT6_ACCESS_RW=y
|
|
||||||
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_LBLAW0=y
|
|
||||||
CONFIG_LBLAW0_BASE=0xFE000000
|
|
||||||
CONFIG_LBLAW0_NAME="FLASH"
|
|
||||||
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
|
||||||
CONFIG_LBLAW1=y
|
|
||||||
CONFIG_LBLAW1_BASE=0xE2400000
|
|
||||||
CONFIG_LBLAW1_NAME="BCSR"
|
|
||||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
|
||||||
CONFIG_ELBC_BR0_OR0=y
|
|
||||||
CONFIG_BR0_OR0_NAME="FLASH"
|
|
||||||
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
||||||
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
||||||
CONFIG_OR0_AM_32_MBYTES=y
|
|
||||||
CONFIG_OR0_XAM_SET=y
|
|
||||||
CONFIG_OR0_SCY_15=y
|
|
||||||
CONFIG_OR0_CSNT_EARLIER=y
|
|
||||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
|
||||||
CONFIG_OR0_XACS_EXTENDED=y
|
|
||||||
CONFIG_OR0_TRLX_RELAXED=y
|
|
||||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
|
||||||
CONFIG_OR0_EAD_EXTRA=y
|
|
||||||
CONFIG_ELBC_BR1_OR1=y
|
|
||||||
CONFIG_BR1_OR1_NAME="BCSR"
|
|
||||||
CONFIG_BR1_OR1_BASE=0xE2400000
|
|
||||||
CONFIG_OR1_XAM_SET=y
|
|
||||||
CONFIG_OR1_SCY_15=y
|
|
||||||
CONFIG_OR1_CSNT_EARLIER=y
|
|
||||||
CONFIG_HID0_FINAL_EMCP=y
|
|
||||||
CONFIG_HID0_FINAL_ICE=y
|
|
||||||
CONFIG_HID2_HBE=y
|
|
||||||
CONFIG_ACR_PIPE_DEP_4=y
|
|
||||||
CONFIG_ACR_RPTCNT_4=y
|
|
||||||
CONFIG_SPCR_TSEC1EP_3=y
|
|
||||||
CONFIG_SPCR_TSEC2EP_3=y
|
|
||||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
|
||||||
CONFIG_LCRR_CLKDIV_4=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=6
|
|
||||||
CONFIG_USE_PREBOOT=y
|
|
||||||
CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_ENV_OVERWRITE=y
|
|
||||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
|
||||||
CONFIG_ENV_ADDR=0xFE080000
|
|
||||||
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
|
|
||||||
CONFIG_DDR_ECC=y
|
|
||||||
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
|
|
||||||
CONFIG_SYS_I2C_LEGACY=y
|
|
||||||
CONFIG_SYS_I2C_FSL=y
|
|
||||||
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
|
|
||||||
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
|
|
||||||
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
|
|
||||||
CONFIG_SYS_I2C_SLAVE=0x7F
|
|
||||||
CONFIG_SYS_I2C_SPEED=400000
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,138 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xFE000000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_SYS_MALLOC_LEN=0x40000
|
|
||||||
CONFIG_SYS_CLK_FREQ=66000000
|
|
||||||
CONFIG_MPC83xx=y
|
|
||||||
CONFIG_HIGH_BATS=y
|
|
||||||
CONFIG_TARGET_MPC8349EMDS_SDRAM=y
|
|
||||||
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
|
|
||||||
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
|
|
||||||
CONFIG_CORE_PLL_RATIO_2_1=y
|
|
||||||
CONFIG_PCI_HOST_MODE_ENABLE=y
|
|
||||||
CONFIG_PCI_INT_ARBITER1_ENABLE=y
|
|
||||||
CONFIG_PCI_INT_ARBITER2_ENABLE=y
|
|
||||||
CONFIG_BOOT_MEMORY_SPACE_LOW=y
|
|
||||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
||||||
CONFIG_TSEC1_MODE_GMII=y
|
|
||||||
CONFIG_TSEC2_MODE_GMII=y
|
|
||||||
CONFIG_BAT0=y
|
|
||||||
CONFIG_BAT0_NAME="SDRAM"
|
|
||||||
CONFIG_BAT0_BASE=0x00000000
|
|
||||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT0_ACCESS_RW=y
|
|
||||||
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT5=y
|
|
||||||
CONFIG_BAT5_NAME="IMMR"
|
|
||||||
CONFIG_BAT5_BASE=0xE0000000
|
|
||||||
CONFIG_BAT5_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT5_ACCESS_RW=y
|
|
||||||
CONFIG_BAT5_ICACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_DCACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT6=y
|
|
||||||
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
|
|
||||||
CONFIG_BAT6_BASE=0xF0000000
|
|
||||||
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT6_ACCESS_RW=y
|
|
||||||
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_LBLAW0=y
|
|
||||||
CONFIG_LBLAW0_BASE=0xFE000000
|
|
||||||
CONFIG_LBLAW0_NAME="FLASH"
|
|
||||||
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
|
||||||
CONFIG_LBLAW1=y
|
|
||||||
CONFIG_LBLAW1_BASE=0xE2400000
|
|
||||||
CONFIG_LBLAW1_NAME="BCSR"
|
|
||||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
|
||||||
CONFIG_LBLAW2=y
|
|
||||||
CONFIG_LBLAW2_BASE=0xF0000000
|
|
||||||
CONFIG_LBLAW2_NAME="SDRAM"
|
|
||||||
CONFIG_LBLAW2_LENGTH_64_MBYTES=y
|
|
||||||
CONFIG_ELBC_BR0_OR0=y
|
|
||||||
CONFIG_BR0_OR0_NAME="FLASH"
|
|
||||||
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
||||||
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
||||||
CONFIG_OR0_AM_32_MBYTES=y
|
|
||||||
CONFIG_OR0_XAM_SET=y
|
|
||||||
CONFIG_OR0_SCY_15=y
|
|
||||||
CONFIG_OR0_CSNT_EARLIER=y
|
|
||||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
|
||||||
CONFIG_OR0_XACS_EXTENDED=y
|
|
||||||
CONFIG_OR0_TRLX_RELAXED=y
|
|
||||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
|
||||||
CONFIG_OR0_EAD_EXTRA=y
|
|
||||||
CONFIG_ELBC_BR1_OR1=y
|
|
||||||
CONFIG_BR1_OR1_NAME="BCSR"
|
|
||||||
CONFIG_BR1_OR1_BASE=0xE2400000
|
|
||||||
CONFIG_OR1_XAM_SET=y
|
|
||||||
CONFIG_OR1_SCY_15=y
|
|
||||||
CONFIG_OR1_CSNT_EARLIER=y
|
|
||||||
CONFIG_ELBC_BR2_OR2=y
|
|
||||||
CONFIG_BR2_OR2_NAME="SDRAM"
|
|
||||||
CONFIG_BR2_OR2_BASE=0xF0000000
|
|
||||||
CONFIG_BR2_PORTSIZE_32BIT=y
|
|
||||||
CONFIG_BR2_MACHINE_SDRAM=y
|
|
||||||
CONFIG_OR2_COLS_9=y
|
|
||||||
CONFIG_OR2_ROWS_13=y
|
|
||||||
CONFIG_OR2_EAD_EXTRA=y
|
|
||||||
CONFIG_HID0_FINAL_EMCP=y
|
|
||||||
CONFIG_HID0_FINAL_ICE=y
|
|
||||||
CONFIG_HID2_HBE=y
|
|
||||||
CONFIG_ACR_PIPE_DEP_4=y
|
|
||||||
CONFIG_ACR_RPTCNT_4=y
|
|
||||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
|
||||||
CONFIG_LCRR_CLKDIV_4=y
|
|
||||||
CONFIG_PCI_ONE_PCI1=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=6
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_ENV_OVERWRITE=y
|
|
||||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
|
||||||
CONFIG_ENV_ADDR=0xFE080000
|
|
||||||
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
|
|
||||||
CONFIG_DDR_ECC=y
|
|
||||||
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
|
|
||||||
CONFIG_SYS_I2C_LEGACY=y
|
|
||||||
CONFIG_SYS_I2C_FSL=y
|
|
||||||
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
|
|
||||||
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
|
|
||||||
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
|
|
||||||
CONFIG_SYS_I2C_SLAVE=0x7F
|
|
||||||
CONFIG_SYS_I2C_SPEED=400000
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,127 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xFE000000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_SYS_MALLOC_LEN=0x40000
|
|
||||||
CONFIG_SYS_CLK_FREQ=66666666
|
|
||||||
CONFIG_MPC83xx=y
|
|
||||||
CONFIG_HIGH_BATS=y
|
|
||||||
CONFIG_TARGET_MPC8349EMDS=y
|
|
||||||
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
|
|
||||||
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
|
|
||||||
CONFIG_CORE_PLL_RATIO_2_1=y
|
|
||||||
CONFIG_PCI_64BIT_MODE_ENABLE=y
|
|
||||||
CONFIG_BOOT_MEMORY_SPACE_LOW=y
|
|
||||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
||||||
CONFIG_TSEC1_MODE_GMII=y
|
|
||||||
CONFIG_TSEC2_MODE_GMII=y
|
|
||||||
CONFIG_BAT0=y
|
|
||||||
CONFIG_BAT0_NAME="SDRAM"
|
|
||||||
CONFIG_BAT0_BASE=0x00000000
|
|
||||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT0_ACCESS_RW=y
|
|
||||||
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT5=y
|
|
||||||
CONFIG_BAT5_NAME="IMMR"
|
|
||||||
CONFIG_BAT5_BASE=0xE0000000
|
|
||||||
CONFIG_BAT5_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT5_ACCESS_RW=y
|
|
||||||
CONFIG_BAT5_ICACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_DCACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT6=y
|
|
||||||
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
|
|
||||||
CONFIG_BAT6_BASE=0xF0000000
|
|
||||||
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT6_ACCESS_RW=y
|
|
||||||
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_LBLAW0=y
|
|
||||||
CONFIG_LBLAW0_BASE=0xFE000000
|
|
||||||
CONFIG_LBLAW0_NAME="FLASH"
|
|
||||||
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
|
||||||
CONFIG_LBLAW1=y
|
|
||||||
CONFIG_LBLAW1_BASE=0xE2400000
|
|
||||||
CONFIG_LBLAW1_NAME="BCSR"
|
|
||||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
|
||||||
CONFIG_ELBC_BR0_OR0=y
|
|
||||||
CONFIG_BR0_OR0_NAME="FLASH"
|
|
||||||
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
||||||
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
||||||
CONFIG_OR0_AM_32_MBYTES=y
|
|
||||||
CONFIG_OR0_XAM_SET=y
|
|
||||||
CONFIG_OR0_SCY_15=y
|
|
||||||
CONFIG_OR0_CSNT_EARLIER=y
|
|
||||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
|
||||||
CONFIG_OR0_XACS_EXTENDED=y
|
|
||||||
CONFIG_OR0_TRLX_RELAXED=y
|
|
||||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
|
||||||
CONFIG_OR0_EAD_EXTRA=y
|
|
||||||
CONFIG_ELBC_BR1_OR1=y
|
|
||||||
CONFIG_BR1_OR1_NAME="BCSR"
|
|
||||||
CONFIG_BR1_OR1_BASE=0xE2400000
|
|
||||||
CONFIG_OR1_XAM_SET=y
|
|
||||||
CONFIG_OR1_SCY_15=y
|
|
||||||
CONFIG_OR1_CSNT_EARLIER=y
|
|
||||||
CONFIG_HID0_FINAL_EMCP=y
|
|
||||||
CONFIG_HID0_FINAL_ICE=y
|
|
||||||
CONFIG_HID2_HBE=y
|
|
||||||
CONFIG_ACR_PIPE_DEP_4=y
|
|
||||||
CONFIG_ACR_RPTCNT_4=y
|
|
||||||
CONFIG_SPCR_TSEC1EP_3=y
|
|
||||||
CONFIG_SPCR_TSEC2EP_3=y
|
|
||||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
|
||||||
CONFIG_LCRR_CLKDIV_4=y
|
|
||||||
CONFIG_PCI_ONE_PCI1=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
|
|
||||||
CONFIG_BOOTDELAY=6
|
|
||||||
CONFIG_USE_PREBOOT=y
|
|
||||||
CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_ENV_OVERWRITE=y
|
|
||||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
|
||||||
CONFIG_ENV_ADDR=0xFE080000
|
|
||||||
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
|
|
||||||
CONFIG_DDR_ECC=y
|
|
||||||
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
|
|
||||||
CONFIG_SYS_I2C_LEGACY=y
|
|
||||||
CONFIG_SYS_I2C_FSL=y
|
|
||||||
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
|
|
||||||
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
|
|
||||||
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
|
|
||||||
CONFIG_SYS_I2C_SLAVE=0x7F
|
|
||||||
CONFIG_SYS_I2C_SPEED=400000
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,130 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xFE000000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_SYS_MALLOC_LEN=0x40000
|
|
||||||
CONFIG_SYS_CLK_FREQ=66000000
|
|
||||||
CONFIG_MPC83xx=y
|
|
||||||
CONFIG_HIGH_BATS=y
|
|
||||||
CONFIG_TARGET_MPC8349EMDS=y
|
|
||||||
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
|
|
||||||
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
|
|
||||||
CONFIG_CORE_PLL_RATIO_2_1=y
|
|
||||||
CONFIG_PCI_HOST_MODE_ENABLE=y
|
|
||||||
CONFIG_PCI_INT_ARBITER1_ENABLE=y
|
|
||||||
CONFIG_PCI_INT_ARBITER2_ENABLE=y
|
|
||||||
CONFIG_BOOT_MEMORY_SPACE_LOW=y
|
|
||||||
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
||||||
CONFIG_TSEC1_MODE_GMII=y
|
|
||||||
CONFIG_TSEC2_MODE_GMII=y
|
|
||||||
CONFIG_BAT0=y
|
|
||||||
CONFIG_BAT0_NAME="SDRAM"
|
|
||||||
CONFIG_BAT0_BASE=0x00000000
|
|
||||||
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT0_ACCESS_RW=y
|
|
||||||
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT0_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT5=y
|
|
||||||
CONFIG_BAT5_NAME="IMMR"
|
|
||||||
CONFIG_BAT5_BASE=0xE0000000
|
|
||||||
CONFIG_BAT5_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT5_ACCESS_RW=y
|
|
||||||
CONFIG_BAT5_ICACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_DCACHE_INHIBITED=y
|
|
||||||
CONFIG_BAT5_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT5_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_BAT6=y
|
|
||||||
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
|
|
||||||
CONFIG_BAT6_BASE=0xF0000000
|
|
||||||
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
|
||||||
CONFIG_BAT6_ACCESS_RW=y
|
|
||||||
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_ICACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
|
|
||||||
CONFIG_BAT6_DCACHE_GUARDED=y
|
|
||||||
CONFIG_BAT6_USER_MODE_VALID=y
|
|
||||||
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
|
||||||
CONFIG_LBLAW0=y
|
|
||||||
CONFIG_LBLAW0_BASE=0xFE000000
|
|
||||||
CONFIG_LBLAW0_NAME="FLASH"
|
|
||||||
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
|
||||||
CONFIG_LBLAW1=y
|
|
||||||
CONFIG_LBLAW1_BASE=0xE2400000
|
|
||||||
CONFIG_LBLAW1_NAME="BCSR"
|
|
||||||
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
|
||||||
CONFIG_ELBC_BR0_OR0=y
|
|
||||||
CONFIG_BR0_OR0_NAME="FLASH"
|
|
||||||
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
||||||
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
||||||
CONFIG_OR0_AM_32_MBYTES=y
|
|
||||||
CONFIG_OR0_XAM_SET=y
|
|
||||||
CONFIG_OR0_SCY_15=y
|
|
||||||
CONFIG_OR0_CSNT_EARLIER=y
|
|
||||||
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
|
||||||
CONFIG_OR0_XACS_EXTENDED=y
|
|
||||||
CONFIG_OR0_TRLX_RELAXED=y
|
|
||||||
CONFIG_OR0_EHTR_8_CYCLE=y
|
|
||||||
CONFIG_OR0_EAD_EXTRA=y
|
|
||||||
CONFIG_ELBC_BR1_OR1=y
|
|
||||||
CONFIG_BR1_OR1_NAME="BCSR"
|
|
||||||
CONFIG_BR1_OR1_BASE=0xE2400000
|
|
||||||
CONFIG_OR1_XAM_SET=y
|
|
||||||
CONFIG_OR1_SCY_15=y
|
|
||||||
CONFIG_OR1_CSNT_EARLIER=y
|
|
||||||
CONFIG_HID0_FINAL_EMCP=y
|
|
||||||
CONFIG_HID0_FINAL_ICE=y
|
|
||||||
CONFIG_HID2_HBE=y
|
|
||||||
CONFIG_ACR_PIPE_DEP_4=y
|
|
||||||
CONFIG_ACR_RPTCNT_4=y
|
|
||||||
CONFIG_SPCR_TSEC1EP_3=y
|
|
||||||
CONFIG_SPCR_TSEC2EP_3=y
|
|
||||||
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
|
||||||
CONFIG_LCRR_CLKDIV_4=y
|
|
||||||
CONFIG_PCI_ONE_PCI1=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=6
|
|
||||||
CONFIG_USE_PREBOOT=y
|
|
||||||
CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_ENV_OVERWRITE=y
|
|
||||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
|
||||||
CONFIG_ENV_ADDR=0xFE080000
|
|
||||||
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
|
|
||||||
CONFIG_DDR_ECC=y
|
|
||||||
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
|
|
||||||
CONFIG_SYS_I2C_LEGACY=y
|
|
||||||
CONFIG_SYS_I2C_FSL=y
|
|
||||||
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
|
|
||||||
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
|
|
||||||
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
|
|
||||||
CONFIG_SYS_I2C_SLAVE=0x7F
|
|
||||||
CONFIG_SYS_I2C_SPEED=400000
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_PROTECTION=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,315 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2006-2010
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mpc8349emds board configuration file
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_E300 1 /* E300 Family */
|
|
||||||
|
|
||||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR Setup
|
|
||||||
*/
|
|
||||||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
|
|
||||||
* unselect it to use old spd_sdram.c
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
|
||||||
#define SPD_EEPROM_ADDRESS1 0x52
|
|
||||||
#define SPD_EEPROM_ADDRESS2 0x51
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
|
|
||||||
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
|
||||||
/*
|
|
||||||
* DDRCDR - DDR Control Driver Register
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
/*
|
|
||||||
* Determine DDR configuration from I2C interface.
|
|
||||||
*/
|
|
||||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
|
|
||||||
#else
|
|
||||||
/*
|
|
||||||
* Manually set up DDR parameters
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
|
|
||||||
#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
|
|
||||||
| CSCONFIG_ROW_BIT_13 \
|
|
||||||
| CSCONFIG_COL_BIT_10)
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
|
|
||||||
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
|
|
||||||
#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
|
|
||||||
|
|
||||||
/* the default burst length is 4 - for 64-bit data path */
|
|
||||||
/* DLL,normal,seq,4/2.5, 4 burst len */
|
|
||||||
#define CONFIG_SYS_DDR_MODE 0x00000022
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM on the Local Bus
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
|
|
||||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FLASH on the Local Bus
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
|
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
|
|
||||||
|
|
||||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
|
||||||
#define CONFIG_SYS_RAMBOOT
|
|
||||||
#else
|
|
||||||
#undef CONFIG_SYS_RAMBOOT
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BCSR register on local bus 32KB, 8-bit wide for MDS config reg
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BCSR 0xE2400000
|
|
||||||
/* Access window base at BCSR base */
|
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
|
||||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial Port
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
|
||||||
|
|
||||||
/* I2C */
|
|
||||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
|
||||||
|
|
||||||
/* SPI */
|
|
||||||
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
|
|
||||||
|
|
||||||
/* GPIOs. Used as SPI chip selects */
|
|
||||||
#define CONFIG_SYS_GPIO1_PRELIM
|
|
||||||
#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
|
|
||||||
#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
|
|
||||||
|
|
||||||
/* TSEC */
|
|
||||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
|
||||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
|
|
||||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
|
||||||
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
|
|
||||||
|
|
||||||
/* USB */
|
|
||||||
#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Addresses are mapped 1-1.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
|
||||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
|
||||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
|
|
||||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
|
|
||||||
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
|
|
||||||
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
|
|
||||||
#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
|
|
||||||
#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
|
|
||||||
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
|
||||||
|
|
||||||
#if !defined(CONFIG_PCI_PNP)
|
|
||||||
#define PCI_ENET0_IOADDR 0xFIXME
|
|
||||||
#define PCI_ENET0_MEMADDR 0xFIXME
|
|
||||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TSEC configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
|
||||||
|
|
||||||
#define CONFIG_GMII 1 /* MII PHY management */
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
|
||||||
#define TSEC1_PHY_ADDR 0
|
|
||||||
#define TSEC2_PHY_ADDR 1
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
|
||||||
|
|
||||||
/* Options are: TSEC[0-1] */
|
|
||||||
#define CONFIG_ETHPRIME "TSEC0"
|
|
||||||
|
|
||||||
#endif /* CONFIG_TSEC_ENET */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure on-board RTC
|
|
||||||
*/
|
|
||||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
|
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment
|
|
||||||
*/
|
|
||||||
#ifndef CONFIG_SYS_RAMBOOT
|
|
||||||
/* Address and size of Redundant Environment Sector */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 256 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
/* Initial Memory map for Linux*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* System performance
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
|
|
||||||
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
|
|
||||||
|
|
||||||
/* System IO Config */
|
|
||||||
#define CONFIG_SYS_SICRH 0
|
|
||||||
#define CONFIG_SYS_SICRL SICRL_LDP_A
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
|
||||||
#define CONFIG_HAS_ETH1
|
|
||||||
#define CONFIG_HAS_ETH0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME "mpc8349emds"
|
|
||||||
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
|
|
||||||
#define CONFIG_BOOTFILE "uImage"
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"hostname=mpc8349emds\0" \
|
|
||||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=${serverip}:${rootpath}\0" \
|
|
||||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
||||||
"addip=setenv bootargs ${bootargs} " \
|
|
||||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
||||||
":${hostname}:${netdev}:off panic=1\0" \
|
|
||||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
|
||||||
"flash_nfs=run nfsargs addip addtty;" \
|
|
||||||
"bootm ${kernel_addr}\0" \
|
|
||||||
"flash_self=run ramargs addip addtty;" \
|
|
||||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
||||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
|
||||||
"bootm\0" \
|
|
||||||
"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
|
|
||||||
"update=protect off fe000000 fe03ffff; " \
|
|
||||||
"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
|
|
||||||
"upd=run load update\0" \
|
|
||||||
"fdtaddr=780000\0" \
|
|
||||||
"fdtfile=mpc834x_mds.dtb\0" \
|
|
||||||
""
|
|
||||||
|
|
||||||
#define NFSBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=$serverip:$rootpath " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
|
||||||
"$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $fdtaddr $fdtfile;" \
|
|
||||||
"bootm $loadaddr - $fdtaddr"
|
|
||||||
|
|
||||||
#define RAMBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $fdtaddr $fdtfile;" \
|
|
||||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
|
|
@ -1,372 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2006-2010
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mpc8349emds board configuration file
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_E300 1 /* E300 Family */
|
|
||||||
|
|
||||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR Setup
|
|
||||||
*/
|
|
||||||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
|
|
||||||
* unselect it to use old spd_sdram.c
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
|
||||||
#define SPD_EEPROM_ADDRESS1 0x52
|
|
||||||
#define SPD_EEPROM_ADDRESS2 0x51
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
|
|
||||||
| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
|
||||||
/*
|
|
||||||
* DDRCDR - DDR Control Driver Register
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
/*
|
|
||||||
* Determine DDR configuration from I2C interface.
|
|
||||||
*/
|
|
||||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
|
|
||||||
#else
|
|
||||||
/*
|
|
||||||
* Manually set up DDR parameters
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
|
|
||||||
#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
|
|
||||||
| CSCONFIG_ROW_BIT_13 \
|
|
||||||
| CSCONFIG_COL_BIT_10)
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
|
|
||||||
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
|
|
||||||
#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
|
|
||||||
|
|
||||||
/* the default burst length is 4 - for 64-bit data path */
|
|
||||||
/* DLL,normal,seq,4/2.5, 4 burst len */
|
|
||||||
#define CONFIG_SYS_DDR_MODE 0x00000022
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM on the Local Bus
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
|
|
||||||
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FLASH on the Local Bus
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
|
|
||||||
|
|
||||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
|
||||||
#define CONFIG_SYS_RAMBOOT
|
|
||||||
#else
|
|
||||||
#undef CONFIG_SYS_RAMBOOT
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BCSR register on local bus 32KB, 8-bit wide for MDS config reg
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BCSR 0xE2400000
|
|
||||||
/* Access window base at BCSR base */
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
|
||||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
|
|
||||||
/*
|
|
||||||
* Base Register 2 and Option Register 2 configure SDRAM.
|
|
||||||
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
|
|
||||||
*
|
|
||||||
* For BR2, need:
|
|
||||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
|
|
||||||
* port-size = 32-bits = BR2[19:20] = 11
|
|
||||||
* no parity checking = BR2[21:22] = 00
|
|
||||||
* SDRAM for MSEL = BR2[24:26] = 011
|
|
||||||
* Valid = BR[31] = 1
|
|
||||||
*
|
|
||||||
* 0 4 8 12 16 20 24 28
|
|
||||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
|
|
||||||
*
|
|
||||||
* For OR2, need:
|
|
||||||
* 64MB mask for AM, OR2[0:7] = 1111 1100
|
|
||||||
* XAM, OR2[17:18] = 11
|
|
||||||
* 9 columns OR2[19-21] = 010
|
|
||||||
* 13 rows OR2[23-25] = 100
|
|
||||||
* EAD set for extra time OR[31] = 1
|
|
||||||
*
|
|
||||||
* 0 4 8 12 16 20 24 28
|
|
||||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* LB sdram refresh timer, about 6us */
|
|
||||||
#define CONFIG_SYS_LBC_LSRT 0x32000000
|
|
||||||
/* LB refresh timer prescal, 266MHz/32 */
|
|
||||||
#define CONFIG_SYS_LBC_MRTPR 0x20000000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
|
|
||||||
| LSDMR_BSMA1516 \
|
|
||||||
| LSDMR_RFCR8 \
|
|
||||||
| LSDMR_PRETOACT6 \
|
|
||||||
| LSDMR_ACTTORW3 \
|
|
||||||
| LSDMR_BL8 \
|
|
||||||
| LSDMR_WRC3 \
|
|
||||||
| LSDMR_CL3)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM Controller configuration sequence.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
|
|
||||||
#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
|
|
||||||
#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
|
|
||||||
#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
|
|
||||||
#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial Port
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
|
|
||||||
|
|
||||||
/* I2C */
|
|
||||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
|
||||||
|
|
||||||
/* SPI */
|
|
||||||
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
|
|
||||||
|
|
||||||
/* GPIOs. Used as SPI chip selects */
|
|
||||||
#define CONFIG_SYS_GPIO1_PRELIM
|
|
||||||
#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
|
|
||||||
#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
|
|
||||||
|
|
||||||
/* TSEC */
|
|
||||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
|
||||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
|
|
||||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
|
||||||
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
|
|
||||||
|
|
||||||
/* USB */
|
|
||||||
#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Addresses are mapped 1-1.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
|
|
||||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
|
||||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
|
|
||||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
|
|
||||||
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
|
|
||||||
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
|
|
||||||
#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
|
|
||||||
#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
|
|
||||||
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
|
||||||
|
|
||||||
#if !defined(CONFIG_PCI_PNP)
|
|
||||||
#define PCI_ENET0_IOADDR 0xFIXME
|
|
||||||
#define PCI_ENET0_MEMADDR 0xFIXME
|
|
||||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TSEC configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
|
||||||
|
|
||||||
#define CONFIG_GMII 1 /* MII PHY management */
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
|
||||||
#define TSEC1_PHY_ADDR 0
|
|
||||||
#define TSEC2_PHY_ADDR 1
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
|
||||||
|
|
||||||
/* Options are: TSEC[0-1] */
|
|
||||||
#define CONFIG_ETHPRIME "TSEC0"
|
|
||||||
|
|
||||||
#endif /* CONFIG_TSEC_ENET */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure on-board RTC
|
|
||||||
*/
|
|
||||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
|
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment
|
|
||||||
*/
|
|
||||||
#ifndef CONFIG_SYS_RAMBOOT
|
|
||||||
/* Address and size of Redundant Environment Sector */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 256 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
/* Initial Memory map for Linux*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* System performance
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
|
|
||||||
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
|
|
||||||
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
|
|
||||||
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
|
|
||||||
|
|
||||||
/* System IO Config */
|
|
||||||
#define CONFIG_SYS_SICRH 0
|
|
||||||
#define CONFIG_SYS_SICRL SICRL_LDP_A
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
|
||||||
#define CONFIG_HAS_ETH1
|
|
||||||
#define CONFIG_HAS_ETH0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME "mpc8349emds"
|
|
||||||
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
|
|
||||||
#define CONFIG_BOOTFILE "uImage"
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"hostname=mpc8349emds\0" \
|
|
||||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=${serverip}:${rootpath}\0" \
|
|
||||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
||||||
"addip=setenv bootargs ${bootargs} " \
|
|
||||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
||||||
":${hostname}:${netdev}:off panic=1\0" \
|
|
||||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
|
||||||
"flash_nfs=run nfsargs addip addtty;" \
|
|
||||||
"bootm ${kernel_addr}\0" \
|
|
||||||
"flash_self=run ramargs addip addtty;" \
|
|
||||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
||||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
|
||||||
"bootm\0" \
|
|
||||||
"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
|
|
||||||
"update=protect off fe000000 fe03ffff; " \
|
|
||||||
"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
|
|
||||||
"upd=run load update\0" \
|
|
||||||
"fdtaddr=780000\0" \
|
|
||||||
"fdtfile=mpc834x_mds.dtb\0" \
|
|
||||||
""
|
|
||||||
|
|
||||||
#define NFSBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=$serverip:$rootpath " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
|
||||||
"$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $fdtaddr $fdtfile;" \
|
|
||||||
"bootm $loadaddr - $fdtaddr"
|
|
||||||
|
|
||||||
#define RAMBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $fdtaddr $fdtfile;" \
|
|
||||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
Loading…
Reference in New Issue