iMX28: Add support for DENX M28EVK board
This contains support for the following components: - DUART - MMC - Both FEC interfaces - NAND - I2C (RTC, EEPROM) - SPI (FLASH) Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
30b9b932a5
commit
fc10272856
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@ -859,6 +859,7 @@ Marek Vasut <marek.vasut@gmail.com>
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palmtc xscale/pxa
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palmtc xscale/pxa
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vpac270 xscale/pxa
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vpac270 xscale/pxa
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zipitz2 xscale/pxa
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zipitz2 xscale/pxa
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m28evk i.MX28
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efikamx i.MX51
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efikamx i.MX51
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efikasb i.MX51
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efikasb i.MX51
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@ -0,0 +1,43 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := m28evk.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,195 @@
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/*
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* DENX M28 module
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mx28_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP0 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
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/* SSP2 clock at 96MHz */
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mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
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return 0;
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}
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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return 0;
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}
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#ifdef CONFIG_CMD_MMC
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static int m28_mmc_wp(int id)
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{
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if (id != 0) {
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printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
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return 1;
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}
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return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
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}
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int board_mmc_init(bd_t *bis)
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{
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/* Configure WP as output */
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gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
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return mxsmmc_initialize(bis, 0, m28_mmc_wp);
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}
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#endif
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#ifdef CONFIG_CMD_NET
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#define MII_OPMODE_STRAP_OVERRIDE 0x16
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#define MII_PHY_CTRL1 0x1e
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#define MII_PHY_CTRL2 0x1f
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int fecmxc_mii_postcall(int phy)
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{
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miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
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miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
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if (phy == 3)
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miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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struct mx28_clkctrl_regs *clkctrl_regs =
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(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
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CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
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CLKCTRL_ENET_TIME_SEL_RMII_CLK);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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printf("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
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if (ret) {
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printf("FEC MXS: Unable to init FEC1\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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printf("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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printf("FEC MXS: Unable to register FEC0 mii postcall\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC1");
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if (!dev) {
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printf("FEC MXS: Unable to get FEC1 device entry\n");
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return -EINVAL;
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}
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ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
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if (ret) {
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printf("FEC MXS: Unable to register FEC1 mii postcall\n");
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return ret;
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}
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return ret;
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}
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#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
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#define MXS_OCOTP_MAX_TIMEOUT 1000000
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void imx_get_mac_from_fuse(char *mac)
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{
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struct mx28_ocotp_regs *ocotp_regs =
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(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
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uint32_t data;
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memset(mac, 0, 6);
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writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
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if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
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MXS_OCOTP_MAX_TIMEOUT)) {
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printf("MXS FEC: Can't get MAC from OCOTP\n");
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return;
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}
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data = readl(&ocotp_regs->hw_ocotp_cust0);
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mac[0] = 0x00;
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mac[1] = 0x04;
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mac[2] = (data >> 24) & 0xff;
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mac[3] = (data >> 16) & 0xff;
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mac[4] = (data >> 8) & 0xff;
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mac[5] = data & 0xff;
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}
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#else
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void imx_get_mac_from_fuse(char *mac)
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{
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memset(mac, 0, 6);
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}
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#endif
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#endif
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@ -158,6 +158,7 @@ tx25 arm arm926ejs tx25 karo
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zmx25 arm arm926ejs zmx25 syteco mx25
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zmx25 arm arm926ejs zmx25 syteco mx25
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imx27lite arm arm926ejs imx27lite logicpd mx27
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imx27lite arm arm926ejs imx27lite logicpd mx27
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magnesium arm arm926ejs imx27lite logicpd mx27
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magnesium arm arm926ejs imx27lite logicpd mx27
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m28evk arm arm926ejs - denx mx28
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nhk8815 arm arm926ejs nhk8815 st nomadik
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nhk8815 arm arm926ejs nhk8815 st nomadik
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nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
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nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
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omap5912osk arm arm926ejs - ti omap
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omap5912osk arm arm926ejs - ti omap
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@ -0,0 +1,282 @@
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/*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __M28_H__
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#define __M28_H__
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#include <asm/arch/regs-base.h>
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/*
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* SoC configurations
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*/
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#define CONFIG_MX28 /* i.MX28 SoC */
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#define CONFIG_MXS_GPIO /* GPIO control */
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#define CONFIG_SYS_HZ 1000 /* Ticks per second */
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/*
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* Define M28EVK machine type by hand until it lands in mach-types
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*/
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#define MACH_TYPE_M28EVK 3613
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#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_ARCH_CPU_INIT
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/*
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* U-Boot Commands
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*/
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#include <config_cmd_default.h>
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_GPIO
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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/*
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* Memory configurations
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* 2 banks of DRAM */
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#define PHYS_SDRAM_1 0x40000000 /* Base address */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
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#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
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#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
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#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Point initial SP in SRAM so SPL can use it too. */
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#define CONFIG_SYS_INIT_SP_ADDR 0x00002000
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/*
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* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
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* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
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* binary. In case there was more of this mess, 0x100 bytes are skipped.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x40000100
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/*
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* U-Boot general configurations
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Print buffer size */
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#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Boot argument buffer size */
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#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
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#define CONFIG_AUTO_COMPLETE /* Command auto complete */
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#define CONFIG_CMDLINE_EDITING /* Command history etc */
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#define CONFIG_SYS_HUSH_PARSER
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||||||
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial Driver
|
||||||
|
*/
|
||||||
|
#define CONFIG_PL011_SERIAL
|
||||||
|
#define CONFIG_PL011_CLOCK 24000000
|
||||||
|
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
|
||||||
|
#define CONFIG_CONS_INDEX 0
|
||||||
|
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MMC Driver
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_CMD_MMC
|
||||||
|
#define CONFIG_MMC
|
||||||
|
#define CONFIG_GENERIC_MMC
|
||||||
|
#define CONFIG_MXS_MMC
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* NAND
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_CMD_NAND
|
||||||
|
#define CONFIG_NAND_MXS
|
||||||
|
#define CONFIG_APBH_DMA
|
||||||
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||||
|
#define CONFIG_SYS_NAND_BASE 0x60000000
|
||||||
|
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||||
|
#define NAND_MAX_CHIPS 8
|
||||||
|
|
||||||
|
/* Environment is in NAND */
|
||||||
|
#define CONFIG_ENV_IS_IN_NAND
|
||||||
|
#define CONFIG_ENV_SIZE (16 * 1024)
|
||||||
|
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||||
|
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||||
|
#define CONFIG_ENV_RANGE (512 * 1024)
|
||||||
|
#define CONFIG_ENV_OFFSET 0x300000
|
||||||
|
#define CONFIG_ENV_OFFSET_REDUND \
|
||||||
|
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
|
||||||
|
|
||||||
|
#define CONFIG_CMD_UBI
|
||||||
|
#define CONFIG_CMD_UBIFS
|
||||||
|
#define CONFIG_CMD_MTDPARTS
|
||||||
|
#define CONFIG_RBTREE
|
||||||
|
#define CONFIG_LZO
|
||||||
|
#define CONFIG_MTD_DEVICE
|
||||||
|
#define CONFIG_MTD_PARTITIONS
|
||||||
|
#define MTDIDS_DEFAULT "nand0=gpmi-nand.0"
|
||||||
|
#define MTDPARTS_DEFAULT \
|
||||||
|
"mtdparts=gpmi-nand.0:" \
|
||||||
|
"3m(bootloader)ro," \
|
||||||
|
"512k(environment)," \
|
||||||
|
"512k(redundant-environment)," \
|
||||||
|
"4m(kernel)," \
|
||||||
|
"-(filesystem)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet on SOC (FEC)
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_CMD_NET
|
||||||
|
#define CONFIG_NET_MULTI
|
||||||
|
#define CONFIG_ETHPRIME "FEC0"
|
||||||
|
#define CONFIG_FEC_MXC
|
||||||
|
#define CONFIG_FEC_MXC_MULTI
|
||||||
|
#define CONFIG_MII
|
||||||
|
#define CONFIG_DISCOVER_PHY
|
||||||
|
#define CONFIG_FEC_XCV_TYPE RMII
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_CMD_I2C
|
||||||
|
#define CONFIG_I2C_MXS
|
||||||
|
#define CONFIG_HARD_I2C
|
||||||
|
#define CONFIG_SYS_I2C_SPEED 400000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EEPROM
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_CMD_EEPROM
|
||||||
|
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||||
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* RTC
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_CMD_DATE
|
||||||
|
/* Use the internal RTC in the MXS chip */
|
||||||
|
#define CONFIG_RTC_INTERNAL
|
||||||
|
#ifdef CONFIG_RTC_INTERNAL
|
||||||
|
#define CONFIG_RTC_MXS
|
||||||
|
#else
|
||||||
|
#define CONFIG_RTC_M41T62
|
||||||
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||||
|
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPI
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_CMD_SPI
|
||||||
|
#define CONFIG_HARD_SPI
|
||||||
|
#define CONFIG_MXS_SPI
|
||||||
|
#define CONFIG_SPI_HALF_DUPLEX
|
||||||
|
#define CONFIG_DEFAULT_SPI_BUS 2
|
||||||
|
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
|
||||||
|
|
||||||
|
/* SPI FLASH */
|
||||||
|
#ifdef CONFIG_CMD_SF
|
||||||
|
#define CONFIG_SPI_FLASH
|
||||||
|
#define CONFIG_SPI_FLASH_STMICRO
|
||||||
|
#define CONFIG_SPI_FLASH_CS 2
|
||||||
|
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||||
|
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||||
|
|
||||||
|
#define CONFIG_ENV_SPI_CS 0
|
||||||
|
#define CONFIG_ENV_SPI_BUS 2
|
||||||
|
#define CONFIG_ENV_SPI_MAX_HZ 24000000
|
||||||
|
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Boot Linux
|
||||||
|
*/
|
||||||
|
#define CONFIG_CMDLINE_TAG
|
||||||
|
#define CONFIG_SETUP_MEMORY_TAGS
|
||||||
|
#define CONFIG_BOOTDELAY 3
|
||||||
|
#define CONFIG_BOOTFILE "uImage"
|
||||||
|
#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "
|
||||||
|
#define CONFIG_BOOTCOMMAND "run bootcmd_net"
|
||||||
|
#define CONFIG_LOADADDR 0x42000000
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Extra Environments
|
||||||
|
*/
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"update_nand_full_filename=u-boot.nand\0" \
|
||||||
|
"update_nand_firmware_filename=u-boot.sb\0" \
|
||||||
|
"update_nand_firmware_maxsz=0x100000\0" \
|
||||||
|
"update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \
|
||||||
|
"update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \
|
||||||
|
"update_nand_get_fcb_size=" /* Get size of FCB blocks */ \
|
||||||
|
"nand device 0 ; " \
|
||||||
|
"nand info ; " \
|
||||||
|
"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
|
||||||
|
"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
|
||||||
|
"update_nand_full=" /* Update FCB, DBBT and FW */ \
|
||||||
|
"if tftp ${update_nand_full_filename} ; then " \
|
||||||
|
"run update_nand_get_fcb_size ; " \
|
||||||
|
"nand scrub -y 0x0 ${filesize} ; " \
|
||||||
|
"nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
|
||||||
|
"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
|
||||||
|
"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
|
||||||
|
"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
|
||||||
|
"fi\0" \
|
||||||
|
"update_nand_firmware=" /* Update only firmware */ \
|
||||||
|
"if tftp ${update_nand_firmware_filename} ; then " \
|
||||||
|
"run update_nand_get_fcb_size ; " \
|
||||||
|
"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
|
||||||
|
"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
|
||||||
|
"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
|
||||||
|
"nand erase ${fcb_sz} ${fw_sz} ; " \
|
||||||
|
"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
|
||||||
|
"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
|
||||||
|
"fi\0"
|
||||||
|
|
||||||
|
#endif /* __M28_H__ */
|
||||||
Loading…
Reference in New Issue