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arm: dts: k3-j721s2: Add support for OSPI Flashes 

J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same and enabled them in SPL and U-Boot.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
[Add partitions information and rebase]
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
This commit is contained in:
Aswath Govindraju 2023-06-01 12:38:32 +05:30 committed by Udit Kumar
parent 566510306c
commit fca79ee428
4 changed files with 262 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
View File

@ -20,6 +20,8 @@
i2c2 = &mcu_i2c1; i2c2 = &mcu_i2c1;
i2c3 = &main_i2c0; i2c3 = &main_i2c0;
ethernet0 = &cpsw_port1; ethernet0 = &cpsw_port1;
spi0 = &ospi0;
spi1 = &ospi1;
}; };
}; };
@ -155,6 +157,34 @@
}; };
}; };
&fss {
bootph-pre-ram;
};
&ospi0 {
bootph-pre-ram;
flash@0 {
bootph-pre-ram;
partitions {
bootph-pre-ram;
partition@3fc0000 {
bootph-pre-ram;
};
};
};
};
&ospi1 {
bootph-pre-ram;
flash@0 {
bootph-pre-ram;
};
};
&serdes_ln_ctrl { &serdes_ln_ctrl {
u-boot,mux-autoprobe; u-boot,mux-autoprobe;
}; };

73
arch/arm/dts/k3-j721s2-common-proc-board.dts
View File

@ -204,6 +204,20 @@
J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>; >;
}; };
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
};
}; };
&main_gpio2 { &main_gpio2 {
@ -401,6 +415,65 @@
num-lanes = <1>; num-lanes = <1>;
}; };
&ospi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "qspi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "qspi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "qspi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "qspi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "qspi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "qspi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mcu_mcan0 { &mcu_mcan0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mcu_mcan0_pins_default>; pinctrl-0 = <&mcu_mcan0_pins_default>;

81
arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
View File

@ -148,6 +148,20 @@
J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>; >;
}; };
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
};
}; };
&sms { &sms {
@ -203,6 +217,73 @@
ti,usb2-only; ti,usb2-only;
}; };
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
&ospi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
reg = <0x0 0x47050000 0x0 0x100>,
<0x0 0x58000000 0x0 0x8000000>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "qspi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "qspi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "qspi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "qspi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "qspi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "qspi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&usb0 { &usb0 {
dr_mode = "otg"; dr_mode = "otg";
maximum-speed = "high-speed"; maximum-speed = "high-speed";

78
arch/arm/dts/k3-j721s2-som-p0.dtsi
View File

@ -138,6 +138,25 @@
}; };
}; };
&wkup_pmx0 {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
>;
};
};
&main_pmx0 { &main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default { main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = < pinctrl-single,pins = <
@ -313,6 +332,65 @@
status = "disabled"; status = "disabled";
}; };
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mcu_r5fss0_core0 { &mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>, memory-region = <&mcu_r5fss0_core0_dma_memory_region>,