imx: support for conga-QMX8 board
Add i.MX8QM qmx8 congatec board support U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Congatec QMX8 Qseven series Board: conga-QMX8 Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9 Boot: SD2 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 switch to partitions #0, OK mmc2 is current device Net: Error: ethernet@5b040000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
This commit is contained in:
Oliver Graute
Stefano Babic
parent
6ac4d44806
commit
fe133eb192
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@ -842,6 +842,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
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dtb-$(CONFIG_ARCH_IMX8) += \
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fsl-imx8qm-apalis.dtb \
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fsl-imx8qm-mek.dtb \
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imx8qm-cgtqmx8.dtb \
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imx8qm-rom7720-a1.dtb \
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fsl-imx8qxp-ai_ml.dtb \
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fsl-imx8qxp-colibri.dtb \
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@ -0,0 +1,404 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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* Copyright 2017 congatec AG
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* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x80000000 0x00020000;
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#include "fsl-imx8qm.dtsi"
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/ {
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model = "Congatec QMX8 Qseven series";
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compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
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stdout-path = &lpuart0;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <3000>;
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};
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reg_usdhc3_vmmc: usdhc3_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <3000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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fsl,rgmii_txc_dly;
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fsl,rgmii_rxc_dly;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@6 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <6>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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};
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};
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};
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&gpio2 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&i2c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c0>;
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clock-frequency = <100000>;
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status = "okay";
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rtc_ext: m41t62@68 {
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compatible = "st,m41t62";
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reg = <0x68>;
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};
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};
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&i2c1 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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status = "okay";
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wm8904: wm8904@1a {
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
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clock-names = "mclk";
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wlf,shared-lrclk;
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/* power-domains = <&pd_mclk_out0>; */
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assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
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<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
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<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
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<&clk IMX8QM_AUD_MCLKOUT0>;
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assigned-clock-rates = <786432000>, <49152000>, <24576000>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx8qm-qmx8 {
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pinctrl_hog: hoggrp{
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fsl,pins = <
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SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021
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SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
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SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021
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SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
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SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
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SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021
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SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
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SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021
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SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
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>;
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};
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pinctrl_lpi2c0: lpi2c0grp {
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fsl,pins = <
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SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c
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SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
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SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_lpuart1: lpuart1grp {
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fsl,pins = <
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SC_P_UART1_RX_DMA_UART1_RX 0x06000020
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SC_P_UART1_TX_DMA_UART1_TX 0x06000020
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SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
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SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
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>;
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};
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pinctrl_lpuart3: lpuart3grp {
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fsl,pins = <
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SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020
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SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020
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>;
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};
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pinctrl_mlb: mlbgrp {
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fsl,pins = <
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SC_P_MLB_SIG_CONN_MLB_SIG 0x21
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SC_P_MLB_CLK_CONN_MLB_CLK 0x21
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SC_P_MLB_DATA_CONN_MLB_DATA 0x21
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>;
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};
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pinctrl_isl29023: isl29023grp {
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fsl,pins = <
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SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
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SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3_gpio: usdhc3grpgpio {
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fsl,pins = <
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SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
|
||||
SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
|
||||
SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart0 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart1 { /* Q7 connector */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pd_dma_lpuart0 {
|
||||
debug_console;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc3_vmmc>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -86,6 +86,12 @@ config TARGET_IMX8QM_MEK
|
|||
select BOARD_LATE_INIT
|
||||
select IMX8QM
|
||||
|
||||
config TARGET_CONGA_QMX8
|
||||
bool "Support congatec conga-QMX8 board"
|
||||
select BOARD_LATE_INIT
|
||||
select SUPPORT_SPL
|
||||
select IMX8QM
|
||||
|
||||
config TARGET_IMX8QM_ROM7720_A1
|
||||
bool "Support i.MX8QM ROM-7720-A1"
|
||||
select BOARD_LATE_INIT
|
||||
|
|
@ -101,6 +107,7 @@ endchoice
|
|||
|
||||
source "board/freescale/imx8qm_mek/Kconfig"
|
||||
source "board/freescale/imx8qxp_mek/Kconfig"
|
||||
source "board/congatec/cgtqmx8/Kconfig"
|
||||
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
|
||||
source "board/toradex/apalis-imx8/Kconfig"
|
||||
source "board/toradex/colibri-imx8x/Kconfig"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
if TARGET_CONGA_QMX8
|
||||
|
||||
config SYS_BOARD
|
||||
default "cgtqmx8"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "congatec"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "cgtqmx8"
|
||||
|
||||
source "board/congatec/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
i.MX8QM CGTQMX8 BOARD
|
||||
M: Oliver Graute <oliver.graute@kococonnector.com>
|
||||
S: Maintained
|
||||
F: board/congatec/cgtqmx8/
|
||||
F: arch/arm/dts/imx8qm-cgtqmx8.dts
|
||||
F: include/configs/cgtqmx8.h
|
||||
F: configs/cgtqmx8_defconfig
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#
|
||||
# Copyright 2017 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += cgtqmx8.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
endif
|
||||
|
|
@ -0,0 +1,460 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 congatec AG
|
||||
* Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <init.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sci/sci.h>
|
||||
#include <asm/arch/imx8-pins.h>
|
||||
#include <usb.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power-domain.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
static iomux_cfg_t uart0_pads[] = {
|
||||
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
void board_late_mmc_env_init(void);
|
||||
void init_clk_usdhc(u32 index);
|
||||
int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* sc_ipc_t ipcHndl = 0; */
|
||||
sc_err_t scierr = 0;
|
||||
|
||||
/* When start u-boot in XEN VM, directly return */
|
||||
/* if (IS_ENABLED(CONFIG_XEN)) */
|
||||
/* return 0; */
|
||||
|
||||
/* ipcHndl = gd->arch.ipc_channel_handle; */
|
||||
|
||||
/* Power up UART0, this is very early while power domain is not working */
|
||||
scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
|
||||
if (scierr != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
/* Set UART0 clock root to 80 MHz */
|
||||
sc_pm_clock_rate_t rate = 80000000;
|
||||
|
||||
scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
|
||||
if (scierr != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
/* Enable UART0 clock root */
|
||||
scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
|
||||
if (scierr != SC_ERR_NONE)
|
||||
return 0;
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX)
|
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
static iomux_cfg_t emmc0[] = {
|
||||
SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
|
||||
SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_cfg_t usdhc1_sd[] = {
|
||||
SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
|
||||
SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_cfg_t usdhc2_sd[] = {
|
||||
SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
|
||||
SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
int i, ret;
|
||||
struct power_domain pd;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-Boot device node) (Physical Port)
|
||||
* mmc0 (onboard eMMC) USDHC1
|
||||
* mmc1 (external SD card) USDHC2
|
||||
* mmc2 (onboard µSD) USDHC3
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
/* onboard eMMC */
|
||||
if (!imx8_power_domain_lookup_name("conn_sdhc0", &pd))
|
||||
power_domain_on(&pd);
|
||||
|
||||
imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
|
||||
init_clk_usdhc(0);
|
||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
/* external SD card */
|
||||
if (!imx8_power_domain_lookup_name("conn_sdhc1", &pd))
|
||||
power_domain_on(&pd);
|
||||
|
||||
imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
|
||||
init_clk_usdhc(1);
|
||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
gpio_request(USDHC1_CD_GPIO, "sd1_cd");
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
break;
|
||||
case 2:
|
||||
/* onboard µSD */
|
||||
if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd))
|
||||
power_domain_on(&pd);
|
||||
|
||||
imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
|
||||
init_clk_usdhc(2);
|
||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
gpio_request(USDHC2_CD_GPIO, "sd2_cd");
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret) {
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = 1;
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_FSL_ESDHC_IMX */
|
||||
|
||||
#if (IS_ENABLED(CONFIG_FEC_MXC))
|
||||
|
||||
#include <miiphy.h>
|
||||
|
||||
static iomux_cfg_t pad_enet0[] = {
|
||||
SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
|
||||
}
|
||||
|
||||
static void enet_device_phy_reset(void)
|
||||
{
|
||||
gpio_set_value(FEC0_RESET, 0);
|
||||
udelay(50);
|
||||
gpio_set_value(FEC0_RESET, 1);
|
||||
|
||||
/* The board has a long delay for this reset to become stable */
|
||||
mdelay(200);
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
setup_iomux_fec();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
/* Reset ENET PHY */
|
||||
enet_device_phy_reset();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_GPIO
|
||||
|
||||
#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
|
||||
#define BKL_ENABLE IMX_GPIO_NR(1, 7)
|
||||
|
||||
static iomux_cfg_t board_gpios[] = {
|
||||
SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
|
||||
SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
|
||||
SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void board_gpio_init(void)
|
||||
{
|
||||
imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
|
||||
|
||||
/* enable LVDS */
|
||||
gpio_request(LVDS_ENABLE, "lvds_enable");
|
||||
gpio_direction_output(LVDS_ENABLE, 1);
|
||||
|
||||
/* enable backlight */
|
||||
gpio_request(BKL_ENABLE, "bkl_enable");
|
||||
gpio_direction_output(BKL_ENABLE, 1);
|
||||
|
||||
/* ethernet reset */
|
||||
gpio_request(FEC0_RESET, "enet0_reset");
|
||||
gpio_direction_output(FEC0_RESET, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: conga-QMX8\n");
|
||||
|
||||
build_info();
|
||||
print_bootinfo();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_XEN))
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_MXC_GPIO
|
||||
board_gpio_init();
|
||||
#endif
|
||||
|
||||
#if (IS_ENABLED(CONFIG_FEC_MXC))
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
puts("\nDDR ");
|
||||
}
|
||||
|
||||
/*
|
||||
* Board specific reset that is system reset.
|
||||
*/
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
/* Use EMMC */
|
||||
if (IS_ENABLED(CONFIG_XEN))
|
||||
return 0;
|
||||
|
||||
return devno;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
/* Use EMMC */
|
||||
if (IS_ENABLED(CONFIG_XEN))
|
||||
return 0;
|
||||
|
||||
return dev_no;
|
||||
}
|
||||
|
||||
extern u32 _end_ofs;
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
env_set("board_name", "QMX8");
|
||||
env_set("board_rev", "iMX8QM");
|
||||
#endif
|
||||
|
||||
env_set("sec_boot", "no");
|
||||
#ifdef CONFIG_AHAB_BOOT
|
||||
env_set("sec_boot", "yes");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
#ifdef IMX_LOAD_HDMI_FIMRWARE
|
||||
char *end_of_uboot;
|
||||
char command[256];
|
||||
|
||||
end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs
|
||||
+ fdt_totalsize(gd->fdt_blob));
|
||||
end_of_uboot += 9;
|
||||
|
||||
/* load hdmitxfw.bin and hdmirxfw.bin*/
|
||||
memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
|
||||
IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
|
||||
|
||||
sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
|
||||
run_command(command, 0);
|
||||
|
||||
sprintf(command, "hdprx load 0x%x",
|
||||
IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
|
||||
run_command(command, 0);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_FASTBOOT
|
||||
#ifdef CONFIG_ANDROID_RECOVERY
|
||||
int is_recovery_key_pressing(void)
|
||||
{
|
||||
return 0; /*TODO*/
|
||||
}
|
||||
#endif /*CONFIG_ANDROID_RECOVERY*/
|
||||
#endif /*CONFIG_FSL_FASTBOOT*/
|
||||
|
||||
/* Only Enable USB3 resources currently */
|
||||
int board_usb_init(int index, enum usb_init_type init)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
|
||||
/* Boot from SD, sector size 0x400 */
|
||||
BOOT_FROM SD 0x400
|
||||
/* SoC type IMX8QM */
|
||||
SOC_TYPE IMX8QM
|
||||
/* Append seco container image */
|
||||
APPEND mx8qm-ahab-container.img
|
||||
/* Create the 2nd container */
|
||||
CONTAINER
|
||||
/* Add scfw image with exec attribute */
|
||||
IMAGE SCU mx8qm-val-scfw-tcm.bin
|
||||
/* Add ATF image with exec attribute */
|
||||
IMAGE A35 bl31.bin 0x80000000
|
||||
/* Add U-Boot image with load attribute */
|
||||
DATA A35 u-boot-dtb.bin 0x80020000
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <spl.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int offset;
|
||||
|
||||
uclass_find_first_device(UCLASS_MISC, &dev);
|
||||
|
||||
for (; dev; uclass_find_next_device(&dev)) {
|
||||
if (device_probe(dev))
|
||||
continue;
|
||||
}
|
||||
|
||||
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
|
||||
while (offset != -FDT_ERR_NOTFOUND) {
|
||||
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
|
||||
NULL, true);
|
||||
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
|
||||
"nxp,imx8-pd");
|
||||
}
|
||||
|
||||
uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
|
||||
|
||||
for (; dev; uclass_find_next_device(&dev)) {
|
||||
if (device_probe(dev))
|
||||
continue;
|
||||
}
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
#if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
if !ARCH_IMX8M && !ARCH_IMX8
|
||||
|
||||
config CHAIN_OF_TRUST
|
||||
depends on !FIT_SIGNATURE && SECURE_BOOT
|
||||
imply CMD_BLOB
|
||||
imply CMD_HASH if ARM
|
||||
select FSL_CAAM
|
||||
select SPL_BOARD_INIT if (ARM && SPL)
|
||||
select SHA_HW_ACCEL
|
||||
select SHA_PROG_HW_ACCEL
|
||||
select ENV_IS_NOWHERE
|
||||
select CMD_EXT4 if ARM
|
||||
select CMD_EXT4_WRITE if ARM
|
||||
bool
|
||||
default y
|
||||
|
||||
config CMD_ESBC_VALIDATE
|
||||
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
|
||||
default y if CHAIN_OF_TRUST
|
||||
help
|
||||
This option enables two commands used for secure booting:
|
||||
|
||||
esbc_validate - validate signature using RSA verification
|
||||
esbc_halt - put the core in spin loop (Secure Boot Only)
|
||||
|
||||
endif
|
||||
|
||||
config VOL_MONITOR_LTC3882_READ
|
||||
depends on VID
|
||||
bool "Enable the LTC3882 voltage monitor read"
|
||||
default n
|
||||
help
|
||||
This option enables LTC3882 voltage monitor read
|
||||
functionality. It is used by common VID driver.
|
||||
|
||||
config VOL_MONITOR_LTC3882_SET
|
||||
depends on VID
|
||||
bool "Enable the LTC3882 voltage monitor set"
|
||||
default n
|
||||
help
|
||||
This option enables LTC3882 voltage monitor set
|
||||
functionality. It is used by common VID driver.
|
||||
|
||||
config USB_TCPC
|
||||
bool "USB Typec port controller simple driver"
|
||||
default n
|
||||
help
|
||||
Enable USB type-c port controller (TCPC) driver
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
MINIMAL=
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
ifdef CONFIG_SPL_INIT_MINIMAL
|
||||
MINIMAL=y
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef MINIMAL
|
||||
# necessary to create built-in.o
|
||||
obj- := __dummy__.o
|
||||
else
|
||||
|
||||
obj-y += mmc.o
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <env.h>
|
||||
#include <command.h>
|
||||
#include <stdbool.h>
|
||||
#include <mmc.h>
|
||||
|
||||
static int check_mmc_autodetect(void)
|
||||
{
|
||||
char *autodetect_str = env_get("mmcautodetect");
|
||||
|
||||
if ((autodetect_str) && (strcmp(autodetect_str, "yes") == 0))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This should be defined for each board */
|
||||
__weak int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
return dev_no;
|
||||
}
|
||||
|
||||
void board_late_mmc_env_init(void)
|
||||
{
|
||||
char cmd[32];
|
||||
char mmcblk[32];
|
||||
u32 dev_no = mmc_get_env_dev();
|
||||
|
||||
if (!check_mmc_autodetect())
|
||||
return;
|
||||
|
||||
env_set_ulong("mmcdev", dev_no);
|
||||
|
||||
/* Set mmcblk env */
|
||||
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
|
||||
mmc_map_to_kernel_blk(dev_no));
|
||||
env_set("mmcroot", mmcblk);
|
||||
|
||||
sprintf(cmd, "mmc dev %d", dev_no);
|
||||
run_command(cmd, 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SPL_SYS_ICACHE_OFF=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_IMX8=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80020000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_TARGET_CONGA_QMX8=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_SPL=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_CMD_CPU=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DM=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_IMX8=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_FEC_MXC_SHARE_MDIO=y
|
||||
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
|
||||
CONFIG_SYS_MMC_ENV_PART=0
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
U-Boot for the Congatec conga-QMX8 board
|
||||
========================================
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Build the ARM Trusted firmware binary
|
||||
- Get scfw_tcm.bin and ahab-container.img
|
||||
- Get imx-mkimage
|
||||
- Build U-Boot
|
||||
- Build imx-mkimage
|
||||
- Flash the binary into the SD card
|
||||
- Boot
|
||||
|
||||
Get and Build the ARM Trusted firmware
|
||||
--------------------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ git clone https://source.codeaurora.org/external/imx/imx-atf
|
||||
$ cd imx-atf/
|
||||
$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
|
||||
$ make PLAT=imx8qm bl31
|
||||
|
||||
Get scfw_tcm.bin and ahab-container.img
|
||||
---------------------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
|
||||
$ chmod +x imx-sc-firmware-1.1.bin
|
||||
$ ./imx-sc-firmware-1.1.bin
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
|
||||
$ chmod +x firmware-imx-8.0.bin
|
||||
$ ./firmware-imx-8.0.bin
|
||||
|
||||
Or use this to avoid running random scripts from the internet,
|
||||
but note that you must agree to the license the script displays:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
|
||||
$ tar -xf imx-sc-firmware-1.1.tar.bz2
|
||||
$ cp imx-sc-firmware-1.1/mx8qx-val-scfw-tcm.bin $(builddir)
|
||||
|
||||
$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
|
||||
$ tar -xf firmware-imx-8.0.tar.bz2
|
||||
$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ export ATF_LOAD_ADDR=0x80000000
|
||||
$ export BL33_LOAD_ADDR=0x80020000
|
||||
$ make cgtqmx8_defconfig
|
||||
$ make u-boot.bin
|
||||
$ make flash.bin
|
||||
|
||||
Flash the binary into the SD card
|
||||
---------------------------------
|
||||
|
||||
Burn the flash.bin binary to SD card offset 32KB:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Congatec
|
||||
========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
cgtqmx8.rst
|
||||
|
|
@ -11,6 +11,7 @@ Board-specific doc
|
|||
AndesTech/index
|
||||
amlogic/index
|
||||
atmel/index
|
||||
congatec/index
|
||||
coreboot/index
|
||||
emulation/index
|
||||
freescale/index
|
||||
|
|
|
|||
|
|
@ -0,0 +1,181 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* Copyright 2018 congatec AG
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CGTQMX8_H
|
||||
#define __CGTQMX8_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_TEXT_BASE 0x0
|
||||
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x013E000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
|
||||
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
|
||||
#define CONFIG_MALLOC_F_ADDR 0x00120000
|
||||
|
||||
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#define CONFIG_OF_EMBED
|
||||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* Flat Device Tree Definitions */
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define USDHC1_BASE_ADDR 0x5B010000
|
||||
#define USDHC2_BASE_ADDR 0x5B020000
|
||||
#define USDHC3_BASE_ADDR 0x5B030000
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
/* Boot M4 */
|
||||
#define M4_BOOT_ENV \
|
||||
"m4_0_image=m4_0.bin\0" \
|
||||
"m4_1_image=m4_1.bin\0" \
|
||||
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
|
||||
"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
|
||||
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
|
||||
"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
|
||||
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
|
||||
#else
|
||||
#define MFG_NAND_PARTITION ""
|
||||
#endif
|
||||
#define FEC0_RESET IMX_GPIO_NR(2, 5)
|
||||
#define FEC0_PDOMAIN "conn_enet0"
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
MFG_NAND_PARTITION \
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
M4_BOOT_ENV \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"panel=NULL\0" \
|
||||
"console=ttyLP0\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x80280000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_2 0x880000000
|
||||
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
|
||||
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
|
||||
|
||||
/* Serial */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
/* Networking */
|
||||
#define CONFIG_FEC_MXC_PHYADDR -1
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#endif /* __CGTQMX8_H */
|
||||
Loading…
Reference in New Issue