diff --git a/arch/arm/include/asm/arch-imx8/image.h b/arch/arm/include/asm/arch-imx8/image.h
index 22592bcdc8..ce6bf67ff0 100644
--- a/arch/arm/include/asm/arch-imx8/image.h
+++ b/arch/arm/include/asm/arch-imx8/image.h
@@ -10,6 +10,7 @@
 #define CONTAINER_HDR_EMMC_OFFSET 0
 #define CONTAINER_HDR_MMCSD_OFFSET SZ_32K
 #define CONTAINER_HDR_QSPI_OFFSET SZ_4K
+#define CONTAINER_HDR_NAND_OFFSET SZ_64M
 
  struct container_hdr{
 	 uint8_t version;
diff --git a/arch/arm/mach-imx/imx8/image.c b/arch/arm/mach-imx/imx8/image.c
index e4417ad1a9..3edf2e385f 100644
--- a/arch/arm/mach-imx/imx8/image.c
+++ b/arch/arm/mach-imx/imx8/image.c
@@ -9,12 +9,14 @@
 #include <dm.h>
 #include <mmc.h>
 #include <spi_flash.h>
+#include <nand.h>
 #include <asm/arch/image.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
 
 #define MMC_DEV		0
 #define QSPI_DEV	1
+#define NAND_DEV	2
 
 static int __get_container_size(ulong addr)
 {
@@ -59,7 +61,6 @@ static int __get_container_size(ulong addr)
 static int get_container_size(void *dev, int dev_type, unsigned long offset)
 {
 	uint8_t *buf = malloc(CONTAINER_HDR_ALIGNMENT);
-	unsigned long count = 0;
 	int ret = 0;
 
 	if (!buf) {
@@ -67,7 +68,9 @@ static int get_container_size(void *dev, int dev_type, unsigned long offset)
 		return -ENOMEM;
 	}
 
+#ifdef CONFIG_SPL_MMC_SUPPORT
 	if (dev_type == MMC_DEV) {
+		unsigned long count = 0;
 		struct mmc *mmc = (struct mmc*)dev;
 		count = blk_dread(mmc_get_blk_desc(mmc), offset/mmc->read_bl_len,
 					CONTAINER_HDR_ALIGNMENT/mmc->read_bl_len, buf);
@@ -75,8 +78,11 @@ static int get_container_size(void *dev, int dev_type, unsigned long offset)
 			printf("Read container image from MMC/SD failed\n");
 			return -EIO;
 		}
+	}
+#endif
+
 #ifdef CONFIG_SPL_SPI_LOAD
-	} else if (dev_type == QSPI_DEV) {
+	if (dev_type == QSPI_DEV) {
 		struct spi_flash *flash = (struct spi_flash *)dev;
 		ret = spi_flash_read(flash, offset,
 					CONTAINER_HDR_ALIGNMENT, buf);
@@ -84,8 +90,18 @@ static int get_container_size(void *dev, int dev_type, unsigned long offset)
 			printf("Read container image from QSPI failed\n");
 			return -EIO;
 		}
-#endif
 	}
+#endif
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	if (dev_type == NAND_DEV) {
+		ret = nand_spl_load_image(offset, CONTAINER_HDR_ALIGNMENT, buf);
+		if (ret != 0) {
+			printf("Read container image from NAND failed\n");
+			return -EIO;
+		}
+	}
+#endif
 
 	ret = __get_container_size((ulong)buf);
 
@@ -116,6 +132,8 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
 		}
 	} else if (dev_type == QSPI_DEV) {
 		offset = CONTAINER_HDR_QSPI_OFFSET;
+	} else if (dev_type == NAND_DEV) {
+		offset = CONTAINER_HDR_NAND_OFFSET;
 	}
 
 	return offset;
@@ -171,3 +189,15 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
 
 	return end/mmc->read_bl_len;
 }
+
+uint32_t spl_nand_get_uboot_raw_page(void)
+{
+	int end;
+
+	end = get_imageset_end((void *)NULL, NAND_DEV);
+	end = ROUND(end, SZ_16K);
+
+	printf("Load image from NAND 0x%x\n", end);
+
+	return end;
+}
diff --git a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
index 0847c3ba11..f162b37646 100644
--- a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
+++ b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
@@ -61,6 +61,74 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
 						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
 
+#ifdef CONFIG_NAND_MXS
+static iomux_cfg_t gpmi_nand_pads[] = {
+	SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+
+	/* i.MX8QXP NAND use nand_re_dqs_pins */
+	SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+
+};
+
+static void setup_iomux_gpmi_nand(void)
+{
+	imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads));
+}
+
+static void imx8qxp_gpmi_nand_initialize(void)
+{
+	int ret;
+#ifdef CONFIG_SPL_BUILD
+	sc_ipc_t ipcHndl = 0;
+
+	ipcHndl = gd->arch.ipc_channel_handle;
+
+	ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_DMA_4_CH0, SC_PM_PW_MODE_ON);
+                        if (ret != SC_ERR_NONE)
+                                return;
+
+
+    ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_NAND, SC_PM_PW_MODE_ON);
+                        if (ret != SC_ERR_NONE)
+                                return;
+#else
+	struct power_domain pd;
+
+	if (!power_domain_lookup_name("conn_dma4_ch0", &pd)) {
+		ret = power_domain_on(&pd);
+		if (ret)
+			printf("conn_dma4_ch0 Power up failed! (error = %d)\n", ret);
+	}
+
+	if (!power_domain_lookup_name("conn_nand", &pd)) {
+		ret = power_domain_on(&pd);
+		if (ret)
+			printf("conn_nand Power up failed! (error = %d)\n", ret);
+	}
+#endif
+
+	init_clk_gpmi_nand();
+	setup_iomux_gpmi_nand();
+	mxs_dma_init();
+
+}
+#endif
+
 static iomux_cfg_t uart0_pads[] = {
 	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -96,6 +164,10 @@ int board_early_init_f(void)
 
 	setup_iomux_uart();
 
+#ifdef CONFIG_NAND_MXS
+	imx8qxp_gpmi_nand_initialize();
+#endif
+
 	return 0;
 }
 
@@ -106,7 +178,7 @@ int board_early_init_f(void)
 #ifndef CONFIG_SPL_BUILD
 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC1_BASE_ADDR, 0, 8},
-#ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2 
+#ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2
 	{USDHC2_BASE_ADDR, 0, 4},
 #endif
 };
@@ -352,59 +424,6 @@ int board_phy_config(struct phy_device *phydev)
 }
 
 
-#ifdef CONFIG_NAND_MXS
-static iomux_cfg_t gpmi_nand_pads[] = {
-	SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_USDHC1_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_USDHC1_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_USDHC1_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-
-	/* i.MX8QXP NAND use nand_re_dqs_pins */
-	SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-	SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
-
-};
-
-static void setup_iomux_gpmi_nand(void)
-{
-	imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads));
-}
-
-static void imx8qm_gpmi_nand_initialize(void)
-{
-	int ret;
-	struct power_domain pd;
-
-	if (!power_domain_lookup_name("conn_dma4_ch0", &pd)) {
-		ret = power_domain_on(&pd);
-		if (ret)
-			printf("conn_dma4_ch0 Power up failed! (error = %d)\n", ret);
-	}
-
-	if (!power_domain_lookup_name("conn_nand", &pd)) {
-		ret = power_domain_on(&pd);
-		if (ret)
-			printf("conn_nand Power up failed! (error = %d)\n", ret);
-	}
-
-	init_clk_gpmi_nand();
-	setup_iomux_gpmi_nand();
-	mxs_dma_init();
-
-}
-#endif
-
 
 static int setup_fec(int ind)
 {
@@ -590,9 +609,6 @@ int board_init(void)
 	setup_fec(CONFIG_FEC_ENET_DEV);
 #endif
 
-#ifdef CONFIG_NAND_MXS
-	imx8qm_gpmi_nand_initialize();
-#endif
 	return 0;
 }
 
diff --git a/board/freescale/imx8qxp_arm2/spl.c b/board/freescale/imx8qxp_arm2/spl.c
index 38258044e3..31ead6faba 100644
--- a/board/freescale/imx8qxp_arm2/spl.c
+++ b/board/freescale/imx8qxp_arm2/spl.c
@@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 	{USDHC1_BASE_ADDR, 0, 8},
-#ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2 
+#ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2
 	{USDHC2_BASE_ADDR, 0, 4},
 #endif
 };
@@ -103,6 +103,7 @@ void spl_dram_init(void)
     /* do nothing for now */
 }
 
+
 int board_mmc_init(bd_t *bis)
 {
 	int i, ret;
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index d075985374..93d4774fff 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -13,15 +13,23 @@
 #include <fdt.h>
 
 #if defined(CONFIG_SPL_NAND_RAW_ONLY)
+uint32_t __weak spl_nand_get_uboot_raw_page(void)
+{
+       return CONFIG_SYS_NAND_U_BOOT_OFFS;
+}
+
 int spl_nand_load_image(struct spl_image_info *spl_image,
 			struct spl_boot_device *bootdev)
 {
 	nand_init();
-
-	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-			    CONFIG_SYS_NAND_U_BOOT_SIZE,
-			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+	nand_spl_load_image(spl_nand_get_uboot_raw_page(),
+						CONFIG_SYS_NAND_U_BOOT_SIZE,
+						(void *)CONFIG_SYS_NAND_U_BOOT_DST);
+#if defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE)
+	spl_set_header_raw_atf(spl_image);
+#else
 	spl_set_header_raw_uboot(spl_image);
+#endif
 	nand_deselect();
 
 	return 0;