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MLK-20583-1 imx: mx6sabresd: Enable OCOTP CTRL clock in DCD and plugin 

The HAB code can not set Field Return and SRK Revoke sticky bits in case
OCOTP CTRL clock is gated out.

In case we disable OCOTP CTRL clock in DCD and plugin those features may
not operate as expected.

Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock
those features, users should use the CSF Unlock command to prevent those
features from being locked.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
This commit is contained in:
Breno Lima 2018-12-13 17:42:55 -02:00 committed by Ye Li
parent f4c76d52da
commit fe78359704
6 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
board/freescale/mx6sabresd/mx6dlsabresd.cfg
View File

@ -136,7 +136,7 @@ DATA 4 0x021b001c 0x00000000
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4070 0x0FFFF000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3

2
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
View File

@ -135,7 +135,7 @@ DATA 4 0x021b001c 0x00000000
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4070 0x0FFFF000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000F3

2
board/freescale/mx6sabresd/mx6qp.cfg
View File

@ -147,7 +147,7 @@ DATA 4, 0x021b001c, 0x00000000
/* set the default clock gate to save power */
DATA 4, 0x020c4068, 0x00C03F3F
DATA 4, 0x020c406c, 0x0030FC03
DATA 4, 0x020c4070, 0x0FFFC000
DATA 4, 0x020c4070, 0x0FFFF000
DATA 4, 0x020c4074, 0x3FF00000
DATA 4, 0x020c4078, 0x00FFF300
DATA 4, 0x020c407c, 0x0F0000F3

2
board/freescale/mx6sabresd/mx6qp_optee.cfg
View File

@ -147,7 +147,7 @@ DATA 4, 0x021b001c, 0x00000000
/* set the default clock gate to save power */
DATA 4, 0x020c4068, 0x00C03F3F
DATA 4, 0x020c406c, 0x0030FC03
DATA 4, 0x020c4070, 0x0FFFC000
DATA 4, 0x020c4070, 0x0FFFF000
DATA 4, 0x020c4074, 0x3FF00000
DATA 4, 0x020c4078, 0x00FFF300
DATA 4, 0x020c407c, 0x0F0000F3

2
board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg
View File

@ -111,7 +111,7 @@ DATA 4, 0x021b001c, 0x00000000
/* set the default clock gate to save power */
DATA 4, 0x020c4068, 0x00C03F3F
DATA 4, 0x020c406c, 0x0030FC03
DATA 4, 0x020c4070, 0x0FFFC000
DATA 4, 0x020c4070, 0x0FFFF000
DATA 4, 0x020c4074, 0x3FF00000
DATA 4, 0x020c4078, 0x00FFF300
DATA 4, 0x020c407c, 0x0F0000C3

2
board/freescale/mx6sabresd/plugin.S
View File

@ -636,7 +636,7 @@
str r1, [r0, #0x068]
ldr r1, =0x0030FC03
str r1, [r0, #0x06c]
ldr r1, =0x0FFFC000
ldr r1, =0x0FFFF000
str r1, [r0, #0x070]
ldr r1, =0x3FF00000
str r1, [r0, #0x074]