Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
fe7f0810dd
2
Makefile
2
Makefile
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@ -350,12 +350,14 @@ endif
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|||
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# enable combined SPL/u-boot/dtb rules for tegra
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ifneq ($(CONFIG_TEGRA),)
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ifeq ($(CONFIG_SPL),y)
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ifeq ($(CONFIG_OF_SEPARATE),y)
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ALL-y += $(obj)u-boot-dtb-tegra.bin
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else
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ALL-y += $(obj)u-boot-nodtb-tegra.bin
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endif
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endif
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endif
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build := -f $(TOPDIR)/scripts/Makefile.build -C
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|
|
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@ -49,33 +49,68 @@ int get_num_cpus(void)
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* Timing tables for each SOC for all four oscillator options.
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*/
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struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
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/* T20: 1 GHz */
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/* n, m, p, cpcon */
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{{ 1000, 13, 0, 12}, /* OSC 13M */
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{ 625, 12, 0, 8}, /* OSC 19.2M */
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{ 1000, 12, 0, 12}, /* OSC 12M */
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{ 1000, 26, 0, 12}, /* OSC 26M */
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/*
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* T20: 1 GHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 22:20 3
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* PLLX_BASE n 17: 8 10
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* PLLX_BASE m 4: 0 5
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* PLLX_MISC cpcon 11: 8 4
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*/
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{
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{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
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{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
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{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
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{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
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},
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/* T25: 1.2 GHz */
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{{ 923, 10, 0, 12},
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{ 750, 12, 0, 8},
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{ 600, 6, 0, 12},
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{ 600, 13, 0, 12},
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/*
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* T25: 1.2 GHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 22:20 3
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* PLLX_BASE n 17: 8 10
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* PLLX_BASE m 4: 0 5
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* PLLX_MISC cpcon 11: 8 4
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*/
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{
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{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
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{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
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{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
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{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
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},
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/* T30: 1.4 GHz */
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{{ 862, 8, 0, 8},
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{ 583, 8, 0, 4},
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{ 700, 6, 0, 8},
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{ 700, 13, 0, 8},
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/*
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* T30: 1.4 GHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 22:20 3
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* PLLX_BASE n 17: 8 10
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* PLLX_BASE m 4: 0 5
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* PLLX_MISC cpcon 11: 8 4
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*/
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{
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{ .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
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{ .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
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{ .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
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{ .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
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},
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/* T114: 1.4 GHz */
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{{ 862, 8, 0, 8},
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{ 583, 8, 0, 4},
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{ 696, 12, 0, 8},
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{ 700, 13, 0, 8},
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/*
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* T114: 700 MHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 23:20 4
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* PLLX_BASE n 15: 8 8
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* PLLX_BASE m 7: 0 8
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*/
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{
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{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
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{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
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{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
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{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
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},
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};
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@ -100,6 +135,7 @@ void adjust_pllp_out_freqs(void)
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int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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u32 divp, u32 cpcon)
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{
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int chip = tegra_get_chip();
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u32 reg;
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/* If PLLX is already enabled, just return */
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@ -116,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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writel(reg, &pll->pll_base);
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|
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/* Set cpcon to PLLX_MISC */
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if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
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reg = (cpcon << PLL_CPCON_SHIFT);
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else
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reg = 0;
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/* Set dccon to PLLX_MISC if freq > 600MHz */
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if (divn > 600)
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|
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@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
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switch (sku_id) {
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case SKU_ID_T33:
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case SKU_ID_T30:
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case SKU_ID_TM30MQS_P_A3:
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return TEGRA_SOC_T30;
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}
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break;
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|
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@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
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enum crc_reset_id {
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/* Things we can hold in reset for each CPU */
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crc_rst_cpu = 1,
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crc_rst_de = 1 << 2, /* What is de? */
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crc_rst_watchdog = 1 << 3,
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crc_rst_debug = 1 << 4,
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crc_rst_de = 1 << 4, /* What is de? */
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crc_rst_watchdog = 1 << 8,
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crc_rst_debug = 1 << 12,
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};
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/**
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@ -65,6 +65,7 @@ enum {
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SKU_ID_T25E = 0x1c,
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SKU_ID_T33 = 0x80,
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SKU_ID_T30 = 0x81, /* Cardhu value */
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SKU_ID_TM30MQS_P_A3 = 0xb1,
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SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
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SKU_ID_T114_1 = 0x01,
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};
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|
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@ -0,0 +1,385 @@
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/*
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* (C) Copyright 2013
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* Avionic Design GmbH <www.avionic-design.de>
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*
|
||||
* SPDX-License-Identifier: GPL-2.0+
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||||
*/
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|
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#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
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#define _PINMUX_CONFIG_TAMONTEN_NG_H_
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|
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#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_DEFAULT, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_##_od, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
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}
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#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
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{ \
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.padgrp = PDRIVE_PINGROUP_##_padgrp, \
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.slwf = _slwf, \
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.slwr = _slwr, \
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.drvup = _drvup, \
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.drvdn = _drvdn, \
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.lpmd = PGRP_LPMD_##_lpmd, \
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.schmt = PGRP_SCHMT_##_schmt, \
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.hsm = PGRP_HSM_##_hsm, \
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}
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static struct pingroup_config tamonten_ng_pinmux_common[] = {
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/* SDMMC1 pinmux */
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DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
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/* SDMMC3 pinmux */
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DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP, NORMAL, INPUT),
|
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DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(GMI_CS6_N, RSVD1, UP, NORMAL, INPUT),
|
||||
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/* SDMMC4 pinmux */
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||||
LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
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LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
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LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* I2C1 pinmux */
|
||||
I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C2 pinmux */
|
||||
I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C3 pinmux */
|
||||
I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* I2C4 pinmux */
|
||||
I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* Power I2C pinmux */
|
||||
I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
|
||||
|
||||
/* UART1 */
|
||||
DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* UART2 */
|
||||
DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* UART3 */
|
||||
DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* UART4 */
|
||||
DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(ULPI_DIR, UARTD, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* DAP */
|
||||
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* I2S1 */
|
||||
DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SPDIF */
|
||||
DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* I2S2 */
|
||||
DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP4 */
|
||||
DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* Tamonten GPIO */
|
||||
DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* LCD */
|
||||
DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* BT656 */
|
||||
LV_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D11, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* GPIOs */
|
||||
DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* LCD BL */
|
||||
DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* SPI4 */
|
||||
DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* Video input GPIO */
|
||||
DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* Sensor GPIO */
|
||||
DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* JTAG */
|
||||
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* Power controls */
|
||||
DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* SPI1 */
|
||||
DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* PMU */
|
||||
DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* PCI */
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* HDMI */
|
||||
DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
};
|
||||
|
||||
static struct pingroup_config unused_pins_lowpower[] = {
|
||||
/* UART1 - NC */
|
||||
DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* UART2 - NC */
|
||||
DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP - NC */
|
||||
DEFAULT_PINMUX(CLK1_REQ, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* DAP4 - NC */
|
||||
DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* Tamonten GPIO - NC */
|
||||
DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* BT656 - NC */
|
||||
LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* GPIO - NC */
|
||||
DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* Video input - NC */
|
||||
DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* KBC keys - NC */
|
||||
DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
|
||||
|
||||
/* PMU - NC */
|
||||
DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* Power rails GPIO - NC */
|
||||
DEFAULT_PINMUX(SPI2_SCK, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
/* Others - NC */
|
||||
DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
static struct padctrl_config tamonten_ng_padctrl[] = {
|
||||
/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
|
||||
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
|
||||
};
|
||||
#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* (C) Copyright 2013
|
||||
* Avionic Design GmbH <www.avionic-design.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/gp_padctrl.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/gpio.h>
|
||||
#include "pinmux-config-tamonten-ng.h"
|
||||
#include <i2c.h>
|
||||
|
||||
#define PMU_I2C_ADDRESS 0x2D
|
||||
|
||||
#define PMU_REG_LDO5 0x32
|
||||
|
||||
#define PMU_REG_LDO_HIGH_POWER 1
|
||||
|
||||
/* Voltage selection for the LDOs with 100mV resolution */
|
||||
#define PMU_REG_LDO_SEL_100(mV) ((((mV - 1000) / 100) + 2) << 2)
|
||||
|
||||
#define PMU_REG_LDO_100(st, mV) (PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV))
|
||||
|
||||
#define PMU_LDO5(st, mV) PMU_REG_LDO_100(st, mV)
|
||||
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_config_table(tamonten_ng_pinmux_common,
|
||||
ARRAY_SIZE(tamonten_ng_pinmux_common));
|
||||
pinmux_config_table(unused_pins_lowpower,
|
||||
ARRAY_SIZE(unused_pins_lowpower));
|
||||
|
||||
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
|
||||
padgrp_config_table(tamonten_ng_padctrl,
|
||||
ARRAY_SIZE(tamonten_ng_padctrl));
|
||||
}
|
||||
|
||||
void gpio_early_init(void)
|
||||
{
|
||||
/* Turn on the alive signal */
|
||||
gpio_request(GPIO_PV2, "ALIVE");
|
||||
gpio_direction_output(GPIO_PV2, 1);
|
||||
|
||||
/* Remove the reset on the external periph */
|
||||
gpio_request(GPIO_PI4, "nRST_PERIPH");
|
||||
gpio_direction_output(GPIO_PI4, 1);
|
||||
}
|
||||
|
||||
void pmu_write(uchar reg, uchar data)
|
||||
{
|
||||
i2c_set_bus_num(4); /* PMU is on bus 4 */
|
||||
i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Do I2C/PMU writes to bring up SD card bus power
|
||||
*
|
||||
*/
|
||||
void board_sdmmc_voltage_init(void)
|
||||
{
|
||||
/* Enable LDO5 with 3.3v for SDMMC3 */
|
||||
pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
|
||||
|
||||
/* Switch the power on */
|
||||
gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
|
||||
gpio_direction_output(GPIO_PJ2, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the MMC muxes, power rails, etc.
|
||||
*/
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
/*
|
||||
* NOTE: We don't do mmc-specific pin muxes here.
|
||||
* They were done globally in pinmux_init().
|
||||
*/
|
||||
|
||||
/* Bring up the SDIO1 power rail */
|
||||
board_sdmmc_voltage_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
#include "tegra30.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Avionic Design Tamonten NG";
|
||||
compatible = "ad,tamonten-ng", "nvidia,tegra30";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@7000c000";
|
||||
i2c1 = "/i2c@7000c700";
|
||||
i2c2 = "/i2c@7000c400";
|
||||
i2c3 = "/i2c@7000c500";
|
||||
i2c4 = "/i2c@7000d000";
|
||||
sdhci0 = "/sdhci@78000600";
|
||||
sdhci1 = "/sdhci@78000400";
|
||||
sdhci2 = "/sdhci@78000000";
|
||||
usb0 = "/usb@7d008000";
|
||||
};
|
||||
|
||||
/* GEN1 */
|
||||
i2c@7000c000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* GEN2 */
|
||||
i2c@7000c400 {
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* CAM */
|
||||
i2c@7000c500 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* DDC */
|
||||
i2c@7000c700 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* PWR */
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* SD slot on the base board */
|
||||
sdhci@78000400 {
|
||||
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 67 0>; /* gpio PI3 */
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
/* EMMC on the COM module */
|
||||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
usb@7d008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "tegra30-tamonten.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Avionic Design Tamonten™ NG Evaluation Carrier";
|
||||
compatible = "ad,tec-ng", "nvidia,tegra30";
|
||||
|
||||
/* GEN2 */
|
||||
i2c@7000c400 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SD card slot */
|
||||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# (C) Copyright 2013
|
||||
# Avionic Design GmbH <www.avionic-design.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
|
||||
|
||||
obj-y := ../common/tamonten-ng.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
|
@ -359,9 +359,10 @@ Active arm armv7 vf610 freescale vf610twr
|
|||
Active arm armv7 zynq xilinx zynq zynq - Michal Simek <monstr@monstr.eu>
|
||||
Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek <monstr@monstr.eu>
|
||||
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
|
||||
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding@avionic-design.de>
|
||||
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding@avionic-design.de>
|
||||
Active arm armv7:arm720t tegra20 avionic-design tec tec - Thierry Reding <thierry.reding@avionic-design.de>
|
||||
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
|
||||
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
|
||||
Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>
|
||||
Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
|
||||
Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
|
||||
Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
|
||||
Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com>
|
||||
|
|
|
|||
|
|
@ -629,3 +629,8 @@ U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
|
|||
U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
|
||||
tegra_i2c_read, tegra_i2c_write,
|
||||
tegra_i2c_set_bus_speed, 100000, 0, 3)
|
||||
#if TEGRA_I2C_NUM_CONTROLLERS > 4
|
||||
U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
|
||||
tegra_i2c_read, tegra_i2c_write,
|
||||
tegra_i2c_set_bus_speed, 100000, 0, 4)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* (C) Copyright 2013
|
||||
* Avionic Design GmbH <www.avionic-design.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "tegra30-common.h"
|
||||
|
||||
/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE tegra30-tec-ng
|
||||
#define CONFIG_OF_CONTROL
|
||||
#define CONFIG_OF_SEPARATE
|
||||
|
||||
/* High-level configuration options */
|
||||
#define V_PROMPT "Tegra30 (TEC-NG) # "
|
||||
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_TEGRA_ENABLE_UARTD
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_TEGRA
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
/* SD/MMC */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_TEGRA_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
|
||||
/* Environment in eMMC, at the end of 2nd "boot sector" */
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_SYS_MMC_ENV_PART 2
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_TEGRA20_SLINK
|
||||
#define CONFIG_TEGRA_SLINK_CTRLS 6
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
|
||||
|
||||
/* USB Host support */
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_TEGRA
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/* USB networking support */
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_SMSC95XX
|
||||
|
||||
/* General networking support */
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_DHCP
|
||||
|
||||
/* Tag support */
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
/* support the new (FDT-based) image format */
|
||||
#define CONFIG_FIT
|
||||
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -82,5 +82,6 @@
|
|||
|
||||
/* For USB EHCI controller */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
||||
|
||||
#endif /* _TEGRA114_COMMON_H_ */
|
||||
|
|
|
|||
|
|
@ -79,5 +79,6 @@
|
|||
|
||||
/* For USB EHCI controller */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
|
||||
|
||||
#endif /* _TEGRA30_COMMON_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue