nbhw18: fixed sgmii link between cpu and ethernet switch
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275706a797
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@ -176,6 +176,16 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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}
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}
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}
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}
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/* TODO: Something with the SERDES polarity seems to be strange
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on NBHW18 V1. Why do we have to swap polarity for
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SERDES0 & SERDES1 to get the SGMII link to the ethernet
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switch working? */
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board_serdes_map[0].swap_rx = 1;
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board_serdes_map[0].swap_tx = 1;
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board_serdes_map[1].swap_rx = 1;
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board_serdes_map[1].swap_tx = 1;
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*serdes_map_array = board_serdes_map;
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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return 0;
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@ -27,7 +27,7 @@
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#define MVSWITCH_GLOBAL2_REG_CMD (0x18)
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#define MVSWITCH_GLOBAL2_REG_CMD (0x18)
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#define MVSWITCH_GLOBAL2_REG_DATA (0x19)
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#define MVSWITCH_GLOBAL2_REG_DATA (0x19)
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/* Temporary FPGA defines -> To be repaced by proper definitions
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/* Temporary FPGA defines -> To be replaced by proper definitions
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as soon as we have the register definition for NBHW18 V2
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as soon as we have the register definition for NBHW18 V2
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*/
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*/
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@ -314,17 +314,21 @@ void configure_mvswitch(void)
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mvswitch_mdio_write(i, 0x04, 0x000f);
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mvswitch_mdio_write(i, 0x04, 0x000f);
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}
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}
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/* Setup port based VLAN to forward only between CPU port and external ports,
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but not between external ports. */
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mvswitch_mdio_write(0x15, 0x06, 0x001F);
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mvswitch_mdio_write(0x15, 0x06, 0x001F);
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for (i = 0x11; i <= 0x14; i++) {
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for (i = 0x11; i <= 0x14; i++) {
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/* Enable forwarding & flooding of unknown addresses on all ethernet ports */
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mvswitch_mdio_write(i, 0x06, 0x0020);
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mvswitch_mdio_write(i, 0x06, 0x0020);
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}
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}
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/* Enable phys */
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/* Enable phys */
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/* TODO: Indirect phy access was used here before -> Should probably no longer be
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/* Indirect phy access is needed to access phys (even in multi chip mode) */
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necessary as all access es are indirect anyway in multi chip mode -> Verify it. */
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for (i = 0x11; i <= 0x14; i++) {
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for (i = 0x11; i <= 0x14; i++) {
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unsigned short smi_value;
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unsigned short smi_value;
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/* Select phy page 0 */
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mvswitch_mdio_write_indirect(i , 0x16, 0x0000);
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if (mvswitch_mdio_read_indirect(i, 0x00, &smi_value) < 0)
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if (mvswitch_mdio_read_indirect(i, 0x00, &smi_value) < 0)
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continue;
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continue;
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smi_value &= ~0x0800;
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smi_value &= ~0x0800;
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@ -95,7 +95,7 @@
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"eth1addr=00:11:22:33:44:55\0" \
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"eth1addr=00:11:22:33:44:55\0" \
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"eth2addr=00:11:22:33:44:56\0" \
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"eth2addr=00:11:22:33:44:56\0" \
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"eth3addr=00:11:22:33:44:57\0" \
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"eth3addr=00:11:22:33:44:57\0" \
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"ethact=ethernet@70000\0" \
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"ethact=ethernet@34000\0" \
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"add_sd_bootargs=setenv bootargs $bootargs root=/dev/mmcblk0p$root_part rootfstype=ext4 console=$consoledev,115200 rootwait loglevel=4\0" \
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"add_sd_bootargs=setenv bootargs $bootargs root=/dev/mmcblk0p$root_part rootfstype=ext4 console=$consoledev,115200 rootwait loglevel=4\0" \
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"add_version_bootargs=setenv bootargs $bootargs\0" \
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"add_version_bootargs=setenv bootargs $bootargs\0" \
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"fdt_skip_update=yes\0" \
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"fdt_skip_update=yes\0" \
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