u-boot

Commit Graph

Author	SHA1	Message	Date
Bai Ping	566b798213	MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip Update the ddrc Qos setting for B1 to align with B0'ssetting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>	2018-11-20 18:21:35 +08:00
Bai Ping	258db72309	MLK-19777-01: imx8mm: rename the lpddr4_ddrphy_train file For LPDDR4 or DDR4, the ddr phy train flow is the same. So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'. make it more common for reuse and move it to driver/ddr/imx8m/. Signed-off-by: Bai Ping <ping.bai@nxp.com>	2018-10-01 17:25:24 +08:00

Author

SHA1

Message

Date

Bai Ping

566b798213

MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip

Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>

2018-11-20 18:21:35 +08:00

Bai Ping

258db72309

MLK-19777-01: imx8mm: rename the lpddr4_ddrphy_train file

For LPDDR4 or DDR4, the ddr phy train flow is the same.
So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'.
make it more common for reuse and move it to driver/ddr/imx8m/.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

2018-10-01 17:25:24 +08:00

2 Commits