commit af7c33c103450e06aecf8adba8cbc8c522295be1 upstream.
During LPDDR initialization we will loop through a series of frequency
changes in order to train at the various operating frequencies. During
this training, accessing the DRAM_CLASS bitfield could happen during a
frequency change and cause the read to hang.
Store the DRAM type into the main structure to avoid multiple readings
while the independent phy is training.
Signed-off-by: Bryan Brattlof <bb@ti.com>
[praneeth@ti.com: cherrypick from v2023.10]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
AM335x uses a special driver "am335x_spl_bch.c" as SPL
NAND loader. This driver expects 1 sector at a time ECC
and doesn't work well with multi-sector ECC that was implemented
in commit 04fcd25873.
Switch back to 1 sector at a time read/ECC.
Fixes: 04fcd25873 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
DSP core is going into abnormal state when load callback is called
after starting of DSP core.
Reload of firmware needs core to be stopped first, followed by
load.
So avoid loading of firmware, when core is started.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Apurva Nandan <a-nandan@ti.com>
Include the static DMA channel data for ti_sci
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
The am62px family of SoCs uses the same DDR controller as found on the
am62ax family. Enable this option when building for the am62px family
Signed-off-by: Bryan Brattlof <bb@ti.com>
Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Include the part number for TI's am62px family of SoCs so we can
properly identify it during boot
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
PLL calibration needs to be enabled when operating in non fractional
mode. Add the sequence to do a fast calibration when using PLL
in this mode.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Tested-by: Neha Malcom Francis <n-francis@ti.com>
AM64x SoCs have two R5F clusters in the main power domain.
Extend support for R5F remote proc driver on AM64x with compatible
strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
spi_nor_read_sfdp() calls nor->read() to read the SFDP data.
The MTD and SPI subsystem expects the tx and rx buf used for
transfers should point to a dma-safe memory.
However, two out of the three calls of spi_nor_read_sfdp() were given
pointers to stack allocated memory as buf argument, hence not in a
dma-safe area.
The third and last call of spi_nor_read_sfdp() was already given a
kmalloc'ed buffer argument, hence dma-safe.
So this patch fixes this issue by introducing a
spi_nor_read_sfdp_dma_unsafe() function which simply wraps the existing
spi_nor_read_sfdp() function and uses some kmalloc'ed memory as a bounce
buffer.
This patch is ported from upstream Linux mtd spi-nor fix commit
bfa4133795e5a0badd402dd3f58b13b3cec64a4b ("mtd: spi-nor: fix DMA unsafe
buffer issue in spi_nor_read_sfdp()")
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Fixes: 0c6f187cdb ("mtd: spi: spi-nor-core: Add SFDP support")
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
On J7 family of devices, the resource management (RM) and power
management (PM) functions run on the MCU domain R5F cores. As a result
it cannot control its own power and reset. That has to be done by the
TIFS firmware.
In the normal case, MCU R5F should be not shut down since it runs the RM
and PM functions. But when the R5F subsystem is booted in split mode,
core 0 will run these functionality, and second core can be shut down or
used for running other firmwares.
During boot, ROM can bring up the boot R5F cores in either lockstep or
split mode based on X509 certificate flags. If booted in lockstep mode,
all R5F cores will run first the R5 SPL, and then once A72 comes up will
run the Device Manager (DM) firmware. But if booted in split mode, core
0 will run DM firmware and second core sits in WFI. Shut it down so that
other firmwares can later be loaded on them. As it is part of cluster that
runs DM, its shut down is handled by TIFS and uses a different TISCI msg
for shut down which sets LPSC R5 register.
Add support for shutting down MCU R5F core1 for Jacinto platforms.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
OSPI0 instance can have multiple flash nodes with same chip select and
node name values. Create a weak alias to give option for adding custom
flash node selection logic for different boards.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
To avoid thermal burn out, program thermal shutdown
value in VTM (Voltage and Thermal Manager) IP.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Neha Francis <n-francis@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
This prevents from getting some 'No USB device found' error,
in usb_ether_init() function for instance.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
commit 7c9267e5115f5cae729a27a0c8ecc35d6297f2b3 upstream.
Approved DT binding has the port mode register in the
"phys" property. Get it from there instead of the custom
"cpsw-phy-sel" property.
This will allow us to keep DT in sync with Linux.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
commit edacf6a44d2383f9137a99ffdf61a24de4a47307 upstream.
The different CPSW sub-system Ethernet ports have different PHY mode
control registers. In order to allow the modes to get configured
independently only the register for the port in question must be
accessed, otherwise we would just be re-configuring the mode for port 1,
while leaving all others at their power-on defaults. Fix this issue by
adding a port-number based offset to the mode control base register
address based on the fact that the control registers for the different
ports are spaced exactly 0x4 bytes apart.
Fixes: 9d0dca1199 ("net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
commit fcb513e5f2396e276653c29098faf4739c588041 upstream.
The approved DT property for MAC efuse (ROM) address is
"ti,syscon-efuse".
Use that and drop custom property "mac_efuse".
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
commit 9b33be392b30deeda242212a0a7b09adc9f91b26 upstream.
The binding represents the MDIO controller as a child device tree
node of the MAC device tree node.
The U-Boot driver mostly ignores that child device tree node and just
hardcodes the resources it uses to support both the MAC and MDIO in a
single driver.
However, some resources like pinctrl muxing states are thus ignored.
This has been a problem with some device trees that will put some
pinctrl states on the MDIO device tree node, like the SK-AM62 Device
Tree does.
Let's rework the driver a bit to create a dummy MDIO driver that we will
then get during our initialization to force the core to select the right
muxing.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
When DDR ECC is off (ecc_reserved_space = 0) k3_ddrss_ddr_fdt_fixup()
doesn't update the DDR size in the memory node of DT. Fix this by
dropping check for ecc_reserved_space to be non zero.
This allows R5 SPL to fixup A53 SPL DT with right DDR size as discovered
during DDR init or based on R5 SPL DT input.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Perform removal of DSS if kconfigs VIDEO_REMOVE or SPL_VIDEO_REMOVE is
set by user. Otherwise if above Kconfigs are not selected, it is assumed
that user wants splash screen to be displayed until linux kernel boots
up. In such scenario, leave the power domain of DSS as "on" so that
splash screen stays intact until kernel boots up.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Change remove method of DSS video driver to disable video port instead
of performing a soft reset, as soft reset takes longer duration. Video
port is disabled by setting enable bit of video port to 0.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
When one of the functions does not support super speed, the composite
driver forces the gadget to high speed. But the speed is never
configured in the cdns3 gadget driver. So configure the speed
in cdns3_gadget_udc_start just like in the kernel.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
MT35XU512ABA has only BFPT and 4-Byte Address Instruction Table
in SFDP. Commit bebdc23750 (" mtd: spi-nor: Parse SFDP SCCR Map")
added checks in spi_nor_octal_dtr_enable() to bail out if the 22nd DWORD
in SCCR does not indicate DTR Octal Mode Enable, since MT35XU512ABA device
supports octal DTR mode, add this property in SFDP fixup.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
If the function is called with no NAND device attached, then this
function can return error value, proceeding further ignoring the same
can cause system crash. This is seen when "mtd list" is run with no NAND
addon cards connected.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
To support u-boot driver model. Retain support legacy way of
doing things if ELM_BASE is defined in <asm/arch/hardware.h>
We could completely get rid of that if all platforms defining
ELM_BASE get rid of that definition. enable CONFIG_SYS_NAND_SELF_INIT
commit 7363cf0581 ("mtd: rawnand: omap_elm: u-boot driver model
support") upstream
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
At first SPI transfers, multiple chip selects can be
enabled simultaneously. This is due to chip select
polarity, which is not properly initialized for all
channels. This patch fixes the issue.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers.
Existing UDMA driver performed the above mentioned configuration
for UDMA. Add similar configuration for PKTDMA here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Expectation of k3_ringacc_ring_reset_raw() is to reset the ring to
requested size and not to 0. Fix this.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Initialize base address of ring config registers required to natively
setup ring cfg registers in the absence of Device Manager (DM) services
at R5 SPL stage.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
RX_FL_CFG message should not be forwarded to TIFS
and should be handled within R5 SPL (when DM services
are not available). Add a no-op function to not handle
RX_FL_CFG messages.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Sec proxy data buffer is 60 bytes with the last of the registers
indicating transmission completion. This however poses a bit of a
challenge.
The backing memory for sec_proxy is regular memory, and all sec proxy
does is to trigger a burst of all 60 bytes of data over to the target
thread backing ring accelerator. It doesn't do a memory scrub when
it moves data out in the burst. When we transmit multiple messages,
remnants of previous message is also transmitted which results in
some random data being set in TISCI fields of messages that have been
expanded forward.
The entire concept of backward compatibility hinges on the fact that
the unused message fields remain 0x0 allowing for 0x0 value to be
specially considered when backward compatibility of message extension
is done.
So, instead of just writing the completion register, we continue
to fill the message buffer up with 0x0 (note: for partial message
involving completion, we already do this).
This allows us to scale and introduce ABI changes back also work with
other boot stages that may have left data in the internal memory.
While at this, drop the unused accessor function.
Fixes: f9aa41023b ("mailbox: Introduce K3 Secure Proxy Driver")
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
This is required since user may want to either call the remove method
of video driver and reset the display or not call the remove method
to continue displaying until next stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
U-boot proper can use frame buffer address passed from SPL to reserve
the memory area used by framebuffer set in SPL so that splash image
set in SPL continues to get displayed while u-boot proper is running.
Put the framebuffer address and size in a bloblist to make them
available at u-boot proper, if in u-boot proper CONFIG_VIDEO is defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
When video is set up in SPL, U-Boot proper needs to use the correct
parameters so it can write to the display.
Put these in a bloblist so they are available to U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
To support video driver at SPL use CONFIG_IS_ENABLED and CONFIG_VAL,
which checks for stage specific configs and thus enables video support
at respective stage.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
To enable TIDSS driver only at SPL stage add rule to compile the TIDSS
video driver.
CONFIG_$(SPL_)VIDEO_TIDSS will compile tidss_drv, at SPL only if
CONFIG_SPL_VIDEO_TIDSS is defined and at u-boot proper if
CONFIG_VIDEO_TIDSS is defined.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To enable video driver at SPL, need to compile video-uclass,
vidconsole-uclass, backlight-uclass, panel-uclass, simple-panel, add
rules to compile them at SPL and u-boot proper. To support
splash_display at SPL, need to compile video-bmp, add rule to compile at
SPL and u-boot proper.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Compile video driver at SPL using CONFIG_SPL_VIDEO.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # qemu-x86_64
Add Kconfigs which enable the video driver and splash screen at SPL
stage only and not at u-boot proper. The existing Kconfigs from u-boot
proper were not used to make SPL splash screen independent to them.
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
On DTR capable flashes like Micron Xcella the writes cannot start or end
at an odd address in DTR mode. Extra 0xff bytes need to be prepended or
appended respectively to make sure both the start and end addresses are
even.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Disable rising edge sampling is set by previous stage. This is
not supported by the driver at the moment
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Update the HyperBus calibration sequence to fix the instabilities
seen during calibration.The current calibration sequence is same
as described in J721E TRM which is as follows:
1) Ensure FIFO RAM Auto-init is complete
2) Attempt to read 64 bytes of data from CFI region
for 16 iterations and if data is same in 4 successive iterations
then consider Delay Locked Loop(DLL) is stabilized.
3) Verify DLL lock by verifying MDLL_LOCK and SDL_LOCK bit set in
CFG_DLL_STAT register.
4) Confirm calibration by checking for "QRY" string in CFI region.
Also perform minor cleanup and update am654_hyperbus_calibrate()
to return non-zero value on failure.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
After performing DFS on A72, the clk-k3 driver causes the reboot to fail
due to fault clock re-initialization
The clk-k3.c driver performs PLL setup based on the difference between
the requested clock rate and current clock rate. If the difference is
found to be more that 50%, in that case it recurses to the clock's parent
for changing its frequency and setting up the PLL. If the difference is
found to be less than that, it assumes that it is a rounding error in the
divider and tries to accommodate for that without touching the parent
clocks.
So, 5% to 50% difference, it assumes it to be a rounding error. From 50%
difference onward it treats it as a HSDIV+PLL configuration case and
sets everything correctly.
So when a fresh boot happens, the A72 clock frequency is found to be at
19.2MHz, which is way less than 2GHz and hence it crosses 50% barrier and
gets properly setup. But when we change the A72 frequency to 1.5 GHz
through DFS, the difference is only of 25% (<50%). So, when we do a
reboot, it doesn't configure the parent clocks and PLLs, it just tries to
make the value close to 2GHz, but that doesn't work.
So, reduce the threshold from 50% to 12.5%, to reconfigure the clocks
correctly at reboot, allowing to boot up after a DFS operation.
Also, check if the parent pll rate is indeed set to target rate, if not
fallback adjusting dividers to get within 5% of requested rate.
This is required to set correct rate for DDR PLLs on AM62A resulting in
lower DDR bandwidth when measured with lmbench (bw_mem)
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
U-Boot is fail to boot class U1 UHS SD cards (such as microcenter)
due to incorrect OTAP and ITAP delay select values. Update OTAP and
ITAP delay select values based on recommeded RIOT values to fix boot
issue.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Udit Kumar
Bryan Brattlof
Roger Quadros
Vignesh Raghavendra
Hari Nagalla
Vishal Mahaveer
Apurva Nandan
Julien Panis
Andreas Dannenberg
Maxime Ripard
Nitin Yadav
Nikhil M Jain
Ravi Gunasekaran
Vaishnav Achath
Kishon Vijay Abraham I
Nishanth Menon
Manorit Chawdhry
Simon Glass
Pratyush Yadav