Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
For LPDDR4 and DDR4, we use the same dram_timing struct
to config parameters. rename the 'lpddr4_timing' to
'dram_timing' for common use.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
For LPDDR4 or DDR4, the ddr phy train flow is the same.
So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'.
make it more common for reuse and move it to driver/ddr/imx8m/.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.
the same method can be use for DDR4. will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
Bai Ping