When switching ARM root clock source from ARM PLL to 24M OSC,
found the ARM timer may stop on few chips during stress reboot test.
The system counter is still increasing, but ARM timer is stopped.
Add a workaround that switch ARM clock source from ARM PLL to
Sys PLL2 500M clock instead of 24M OSC. Stress reboot test is
passed on all failed chips.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 74770228976c013a3e289b21f6e27334ea97bee4)
According to iMX8MM DRAM PLL spec, the Fvco range is from 1600Mhz to 3200Mhz,
and (Fin / P) range is from 6Mhz to 25Mhz. However, our current PLL settings
violates the spec.
This patch changes the dividers to meet the spec requirement.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 3b303840f625121c08898f4c43cf29cf2a2d0170)
Current flexspi clock root is set to 25Mhz OSC, but the flash can support
to 166Mhz clock, so change the flexspi clock root to system PLL1 100Mhz
clock to increase speed.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
ipg_stop from GPC is not connected to WDOG directly, the sec_debug clock is
used to sample the ipg_stop from GPC. So when this clock is off, ipg_stop input
of WDOG can’t assert, WDOG will fail to stop in DSM mode.
Enable this clock forever in SPL, so other SW don't need to touch it.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 1da6c9b3a837d15c25086af449462d5e8b56c290)
Now fsl_esdhc driver require the index of USDHCx_CLK_ROOT should be
defined sequentially. otherwise driver may get the wrong usdhc root
clock.
e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT
This patch add MXC_XXX_CLK, map to the real defined clock index.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60)
Conflicts:
arch/arm/cpu/armv8/imx8m/clock_imx8mm.c
Enable the video PLL (594Mhz) and clocks in displaymix. Add the LCDIF clock
set interface to change its dot clock rate.
Update registers header file for LCDIF base address.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 3c27bc4bfa35dbebee2b5797c9137a2257946eca)
According to ADD, the target frequency for NOC bus clock is 750Mhz,
the default setting from ROM is selecting the PLL1_800M_clk as source.
This patch sets the PLL3 to 750Mhz and select it as the source of NOC
clock root.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit dc53b0d89b044e387779d4751dd4c7d3bfe0d0a9)
The DRAM PLL generates clock to both DRAM controller & PHY, from 166.7MHz to 800MHz.
So it can't be used when we need lower DDR frequency.
The DRAM PHY supports a bypass mode to allow lower frequency operation from DDR-50 to
DDR-666. In this mode, the PLL inside PHY is disabled, the PHY clock is provided externally
as BypassPclk which is generated from dram_alt_clk_root.
We add APIs for this bypass mode, to support frequencies for DDR-100, DDR-250 and DDR-400,
which are needed when training DDR4.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 323b7377dd3babc03f883355c140690259dd12d5)
The GIC clock rate has some limitation, it should be
set to higher than 100MHz when NOC frequency is set to
the highest frequency. So switch the GIC clock source
to sys_pll2_100mhz.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit bd4cfcb391389287894bb5cd715be0a67f6332cf)
Enable the OTG power on, add clock fuction and USB base address.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit d4f12cd92b18283daca35b35339a96c557f5127c)
The PLL used on i.MX8MM is different from i.MX8MQ,
so add new clock_imx8mm.c dedicated for i.MX8MM,
Currently use two new files for i.MX8MM, in future
the code could be restructed to share to avoid
code duplication.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 4415e28950b1baf62a9b9e3c819d93e7deba0cad)
Ye Li
Haibo Chen
Bai Ping
Peng Fan