In flexspi driver, each sf command will disable the module in release bus
function. So reading from flexspi memory-map address using "md" command
can't work. When iMX8MM kicks M4 image to run flexspi NOR XIP,
this causes problem.
Signed-off-by: Ye Li <ye.li@nxp.com>
The address size is 3 bytes when using BAR mode, but the driver
supposes the 4bytes mode is enabled and uses 4 bytes address. This
cause address issue.
Also the mask needs set to 23bits for 3 bytes address.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 2e9a9e0fe379306f7c1065f9afa9e67386be2503)
If not initialize unused LUT to 0, the value is random which might
cause qspi command failure.
On i.MX8QM/QXP, it works ok because ROM inittialize them to 0, but on
i.MX8MM, ROM not initialize them, so let's do it here.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit c4bd49c7b249073415f052fb28cd5a4ad374a318)
When the power domain driver is enabled, we need to enable clocks after power
domain on. The clock settings in board level codes must be removed, needs to
set them when the device is probed. Add this weak function in flexspi driver,
that SoC codes can implement the clock settings.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit a4d334e70839021a50dca2ad4ad98ecee16081f9)
i.MX8QM ROM didn't calculate the DLL correctly in some cases, to avoid
the wrong DLL setting impact the following functions, reset them to the
default value when probe.
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit da3c2a9f09afa45a428809b7bf3f981a1ccb7f2e)
Update the LUT settings, spi_xfer to use the 4bytes address read/write/erase
commands.
Also add a function to enter the 4bytes mode for flash device.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 704c1c357d5566e6b3a72c57427d90ba08f9ef0f)
Add fsl_fspi driver for flexspi controller. This driver supports:
1. DDR Quad output
2. Prefetch function for improve read performance.
3. Fast read and Quad read for one line read mode.
4. Read flash FSR register.
5. DM.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa)
Luo Ji
Ye Li
Peng Fan
Han Xu