u-boot

Commit Graph

Author	SHA1	Message	Date
Conor Dooley	540d02217f	dt-bindings: clk: add missing clk ids for microchip mpfs When this binding header was initally upstreamed, the PLL clocking the microprocessor subsystem (MSS) and the RTC reference clocks were omitted. Add them now, matching the IDs used in Linux. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>	2022-11-15 15:37:17 +08:00
Padmarao Begari	2f27c9219e	clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>	2021-01-18 11:06:38 +08:00

Author

SHA1

Message

Date

Conor Dooley

540d02217f

dt-bindings: clk: add missing clk ids for microchip mpfs

When this binding header was initally upstreamed, the PLL clocking the
microprocessor subsystem (MSS) and the RTC reference clocks were
omitted. Add them now, matching the IDs used in Linux.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>

2022-11-15 15:37:17 +08:00

Padmarao Begari

2f27c9219e

clk: Add Microchip PolarFire SoC clock driver

Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>

2021-01-18 11:06:38 +08:00

2 Commits